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1. 发明授权

US06623911B1 Method to form code marks on mask ROM products 有权
标题翻译：在掩码ROM产品上形成代码标记的方法
公开(公告)号：US06623911B1
公开(公告)日：2003-09-23
申请号：US09953524
申请日：2001-09-17
申请人： Yu-Chang Jong , Tai-Yuan Wu
发明人： Yu-Chang Jong , Tai-Yuan Wu
IPC分类号： G03F720
CPC分类号： H01L23/544 , G03F7/203 , H01L2223/54433 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.
摘要翻译：描述了通过向普通光刻工艺添加额外的暴露步骤来形成独立于后端平面化的清晰代码标记的方法。待图案化的层设置在基板上。将光致抗蚀剂层涂覆在待图案化的层上。光致抗蚀剂层首先通过代码掩模曝光，并通过图案掩模曝光。显影光致抗蚀剂层以形成具有来自编码掩模的码标图案和来自图案化掩模的器件图案的光致抗蚀剂掩模。要被图案化的层被蚀刻掉，其不被光致抗蚀剂掩模覆盖，以在集成电路器件的制造中同时形成器件结构和代码标记。

2. 发明授权

US07608889B2 Lateral diffusion metal-oxide-semiconductor structure 有权
标题翻译：侧向扩散金属氧化物半导体结构
公开(公告)号：US07608889B2
公开(公告)日：2009-10-27
申请号：US11864278
申请日：2007-09-28
申请人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
发明人： Dah-Chuen Ho , Chien-Shao Tang , Zhe-Yi Wang , Yu-Chang Jong
IPC分类号： H01L29/78
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/4933 , H01L29/66659
摘要： A lateral diffusion metal-oxide-semiconductor (LDMOS) structure comprises a gate, a source, a drain and a shallow trench isolation. The shallow trench isolation is formed between the drain and the gate to withstand high voltages, applied to the drain, and is associated with the semiconductor substrate to form a recess. As such, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate. Optionally, the surface of the shallow trench isolation is lower than the surface of the semiconductor substrate by 300-1500 angstroms.
摘要翻译：横向扩散金属氧化物半导体（LDMOS）结构包括栅极，源极，漏极和浅沟槽隔离。浅沟槽隔离形成在漏极和栅极之间以承受施加到漏极上的高电压，并且与半导体衬底相关联以形成凹部。因此，浅沟槽隔离的表面低于半导体衬底的表面。可选地，浅沟槽隔离的表面比半导体衬底的表面低300-1500埃。

3. 发明授权

US07081662B1 ESD protection device for high voltage 有权
标题翻译：高压ESD保护装置
公开(公告)号：US07081662B1
公开(公告)日：2006-07-25
申请号：US11199833
申请日：2005-08-09
申请人： Jian-Hsing Lee , Yu-Chang Jong
发明人： Jian-Hsing Lee , Yu-Chang Jong
IPC分类号： H01L29/00 , H01L29/73
CPC分类号： H01L27/0259
摘要： An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.
摘要翻译：提供一种静电放电（ESD）保护结构及其形成方法。该结构包括具有掩埋层的衬底以及掩埋层上的第一和第二高压阱区。第一和第二高电压阱区具有相反的导电类型并且物理上彼此接触。该结构还包括从第一高电压阱区域延伸到第二高电压阱区域的场区域，第一高压阱区域中的第一掺杂区域和与场区域物理接触的第二掺杂区域，第二高压井区域并物理接触场区域。第一和第二掺杂区域和第一高电压阱区域形成可以保护集成电路免受ESD的双极晶体管。

4. 发明授权

US08324705B2 Schottky diodes having low-voltage and high-concentration rings 有权
标题翻译：具有低电压和高浓度环的肖特基二极管
公开(公告)号：US08324705B2
公开(公告)日：2012-12-04
申请号：US12127629
申请日：2008-05-27
申请人： Chien-Shao Tang , Dah-Chuen Ho , Yu-Chang Jong , Zhe-Yi Wang , Yuh-Hwa Chang , Yogendra Yadav
发明人： Chien-Shao Tang , Dah-Chuen Ho , Yu-Chang Jong , Zhe-Yi Wang , Yuh-Hwa Chang , Yogendra Yadav
IPC分类号： H01L29/872
CPC分类号： H01L27/0629 , H01L29/0619 , H01L29/0649 , H01L29/872
摘要： An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底上的第一导电类型的第一阱区; 与第一导电类型相反的第二导电类型的环绕第一阱区的第二阱区; 以及在所述第一阱区上并邻接所述第一阱区并且在所述第二阱区的至少内部部分上延伸的含金属层。含金属层和第一阱区形成肖特基势垒。所述集成电路结构还包括环绕所述含金属层的隔离区域; 以及第二导电类型的第三阱区域，其环绕至少第一阱区域的中心部分。第三阱区域具有比第二阱区域更高的杂质浓度，并且包括邻近含金属层的顶表面和高于第一阱区域和第二阱区域的底表面的底表面。

5. 发明申请

US20070267693A1 SUPPRESSION OF HOT-CARRIER EFFECTS USING DOUBLE WELL FOR THIN GATE OXIDE LDMOS EMBEDDED IN HV PROCESS 有权
标题翻译：在高压工艺中嵌入薄壁氧化物LDMOS的双载体效应的抑制
公开(公告)号：US20070267693A1
公开(公告)日：2007-11-22
申请号：US11419685
申请日：2006-05-22
申请人： Hsing-Yi Chien , Yu-Chang Jong , Ruey-Hsin Liu , Te-Yin Hsia
发明人： Hsing-Yi Chien , Yu-Chang Jong , Ruey-Hsin Liu , Te-Yin Hsia
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42364 , H01L29/7816
摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
摘要翻译：半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。

6. 发明授权

US07129559B2 High voltage semiconductor device utilizing a deep trench structure 有权
公开(公告)号：US07129559B2
公开(公告)日：2006-10-31
申请号：US10821432
申请日：2004-04-09
申请人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
发明人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
IPC分类号： H01L29/00
CPC分类号： H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.

7. 发明申请

US20050081824A1 Contaminant particle removal by optical tweezers 失效
标题翻译：通过光学镊子去除污染物
公开(公告)号：US20050081824A1
公开(公告)日：2005-04-21
申请号：US10689430
申请日：2003-10-20
申请人： Hong-Miao Chen , Yu-Chang Jong , Huan-Chi Tseng
发明人： Hong-Miao Chen , Yu-Chang Jong , Huan-Chi Tseng
IPC分类号： B08B6/00 , B08B7/00 , C25F1/00 , C25F3/30 , C25F5/00 , F02D1/00 , H01L21/02 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： B08B7/0042 , H01L21/02046 , Y10S438/906
摘要： The invention describes how contaminant particles may be removed from a surface without in any way damaging that surface. First, the positional co-ordinates of all particles on the surface are recorded. Optionally, only particles that can be expected to cause current or future damage to the surface are included. Then, using optical tweezers, each particle is individually removed and then disposed of. Six different ways to remove and dispose of particles are described.
摘要翻译：本发明描述了如何从表面去除污染物颗粒，而不会以任何方式损坏该表面。首先，记录表面上所有颗粒的位置坐标。可选地，仅包括可以预期会对表面造成当前或未来损害的颗粒。然后，使用光学镊子，分别除去每个颗粒，然后处理。描述了去除和处理颗粒的六种不同的方法。

8. 发明授权

US08004038B2 Suppression of hot-carrier effects using double well for thin gate oxide LDMOS embedded in HV process 有权
标题翻译：使用双阱抑制热载流子效应，用于嵌入HV工艺的薄栅极氧化物LDMOS
公开(公告)号：US08004038B2
公开(公告)日：2011-08-23
申请号：US11419685
申请日：2006-05-22
申请人： Hsing-Yi Chien , Yu-Chang Jong , Te-Yin Hsia , Ruey-Shin Liu
发明人： Hsing-Yi Chien , Yu-Chang Jong , Te-Yin Hsia , Ruey-Shin Liu
IPC分类号： H01L31/062
CPC分类号： H01L29/7835 , H01L21/823892 , H01L27/0922 , H01L29/0653 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42364 , H01L29/7816
摘要： A semiconductor device includes a first high-voltage well having a first dopant disposed in a semiconductor substrate; a second high-voltage well having a second dopant disposed in the semiconductor substrate, laterally adjacent to the first high-voltage well; a low-voltage well having the second dopant disposed overlying the second high-voltage well; a drain region having the first dopant disposed in the first high-voltage well; a source having the first dopant disposed in the low-voltage well; and a gate disposed on the semiconductor substrate and laterally between the source and the drain, wherein the gate includes a thin gate dielectric and a gate electrode.
摘要翻译：半导体器件包括：第一高电压阱，其具有设置在半导体衬底中的第一掺杂物; 第二高电压阱，具有设置在半导体衬底中的第二掺杂剂，与第一高压阱横向相邻; 具有设置在第二高压井上的第二掺杂剂的低电压阱; 漏极区，其具有设置在所述第一高压阱中的所述第一掺杂物; 具有设置在低压井中的第一掺杂物的源; 以及设置在所述半导体衬底上并且在所述源极和漏极之间的横向的栅极，其中所述栅极包括薄栅极电介质和栅电极。

9. 发明授权

US07482662B2 High voltage semiconductor device utilizing a deep trench structure 有权
标题翻译：利用深沟槽结构的高压半导体器件
公开(公告)号：US07482662B2
公开(公告)日：2009-01-27
申请号：US11554368
申请日：2006-10-30
申请人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
发明人： Chen-Bau Wu , Shun-Liang Hsu , You-Kuo Wu , Yu-Chang Jong
IPC分类号： H01L27/088
CPC分类号： H01L29/0653 , H01L29/0692 , H01L29/456 , H01L29/4933 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a substrate having a source, a drain, and a gate between the source and the drain. Both the source and the drain include a first edge, and the gate includes a first portion. A first deep trench structure is situated under the first portion of the gate and proximate to the first edge of the source and the first edge of the drain.
摘要翻译：半导体器件包括在源极和漏极之间具有源极，漏极和栅极的衬底。源极和漏极都包括第一边缘，并且栅极包括第一部分。第一深沟槽结构位于栅极的第一部分下方并且靠近源极的第一边缘和漏极的第一边缘。

10. 发明授权

US07372083B2 Embedded silicon-controlled rectifier (SCR) for HVPMOS ESD protection 有权
标题翻译：嵌入式可控硅整流器（SCR），用于HVPMOS ESD保护
公开(公告)号：US07372083B2
公开(公告)日：2008-05-13
申请号：US11199662
申请日：2005-08-09
申请人： Jian-Hsing Lee , Yu-Chang Jong
发明人： Jian-Hsing Lee , Yu-Chang Jong
IPC分类号： H01L29/72
CPC分类号： H01L29/7393 , H01L27/0262 , H01L29/0653 , H01L29/0696 , H01L29/7436
摘要： A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.
摘要翻译：提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中，第一源极/漏极区域。该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。该器件具有强大的正向和反向模式ESD性能。

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