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1. 发明申请

US20110055528A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20110055528A1
公开(公告)日：2011-03-03
申请号：US12844800
申请日：2010-07-27
申请人： Yuki KONDOH , Tohru Nojiri
发明人： Yuki KONDOH , Tohru Nojiri
IPC分类号： G06F9/318
CPC分类号： G06F9/30101 , G06F9/3824 , G06F12/1458
摘要： The data processor can form a system including a combination of two or more operating systems running in parallel, which achieves a higher data transfer rate between operating systems and the increase in system performance without impairing the system reliability. In the system, data transfer between domains is performed in an enhanced access mode as well as an access mode in which an access from a domain manager having control of domains is handled as one from the domain manager. The enhanced access mode is arranged by enhancing, to a CPU scale, an access mode in which an access from the domain manager is treated as an access from a software program working on a domain, and the software program of domain manager transfers data between the domains. For example, in case that the domain manager performs data transfer between domains in the enhanced access mode, a read access from the domain manager is disguised as a read access from a first domain, and a write access from the domain manager is disguised as a write access from a second domain.
摘要翻译：数据处理器可以形成包括并行运行的两个或多个操作系统的组合的系统，其在操作系统之间实现更高的数据传输速率，并且在不损害系统可靠性的情况下提高系统性能。在系统中，域之间的数据传输以增强的访问模式以及访问模式进行，其中来自具有域的控制的域管理员的访问被从域管理器处理为一个。通过将来自域管理器的访问视为来自在域上工作的软件程序的访问的访问模式，增强访问模式被设置为CPU规模，并且域管理器的软件程序在域名例如，如果域管理器在增强访问模式下执行域之间的数据传输，则来自域管理器的读取访问被伪装成来自第一域的读取访问，并且来自域管理器的写入访问被伪装为从第二个域写入访问。

2. 发明授权

US5179685A Information processing apparatus 失效
标题翻译：信息处理装置
公开(公告)号：US5179685A
公开(公告)日：1993-01-12
申请号：US372696
申请日：1989-06-28
申请人： Tohru Nojiri
发明人： Tohru Nojiri
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/5016 , G06F9/462
摘要： An information processing apparatus for managing a storage such as a register file divided into a plurality of register banks. A register bank pointer is provided for each register bank in the register file so as to link the register bank to another optional register bank. The activation records for each of a plurality of tasks are allocated to the corresponding register banks in the register file. The necessary number of register banks for the allocation of the activation records for each task are linked together. The number of register banks linked together or released from the linking is changed with the increase and decrease of the number of activation records to be allocated for each task.
摘要翻译：一种用于管理分成多个寄存器组的诸如寄存器文件的存储的信息处理装置。为寄存器文件中的每个寄存器组提供寄存器组指针，以将寄存器组链接到另一个可选的寄存器组。多个任务中的每一个的激活记录被分配给寄存器文件中的对应的寄存器组。为每个任务分配激活记录的必要数量的寄存器组链接在一起。链接在一起或从链接释放的寄存器组的数量随着为每个任务分配的激活记录的数量的增加和减少而改变。

3. 发明授权

US08813070B2 Data processor with interfaces for peripheral devices 有权
标题翻译：具有外围设备接口的数据处理器
公开(公告)号：US08813070B2
公开(公告)日：2014-08-19
申请号：US12958687
申请日：2010-12-02
申请人： Tohru Nojiri , Yuki Kondoh
发明人： Tohru Nojiri , Yuki Kondoh
IPC分类号： G06F9/455 , G06F13/10
CPC分类号： G06F9/45533 , G06F9/4411 , G06F9/45541 , G06F13/102 , G06F13/105
摘要： This invention is intended to reduce the hypervisor overhead. In the data processor disclosed herein, when a device driver calls for access to a control register to activate a process of a dedicated controlled peripheral device, the access is handled directly without intervention of processing by the hypervisor. When an interrupt is generated from a dedicated controlled peripheral device, a process is directly initiated by the device driver of the operating system governing the peripheral device without intervention of processing by the hypervisor. By implementing this manner of control in the processor, it becomes possible to carry out peripheral device control without intervention of processing by the hypervisor. Thereby, the hypervisor overhead is alleviated.
摘要翻译：本发明旨在减少管理程序开销。在本文公开的数据处理器中，当设备驱动程序要求访问控制寄存器以激活专用受控外围设备的处理时，直接处理访问，而不用管理程序进行处理。当从专用的受控外围设备产生中断时，由管理外围设备的操作系统的设备驱动程序直接发起一个过程，而不会由管理程序进行处理。通过在处理器中实现这种控制方式，可以在不经管理程序处理的情况下执行外围设备控制。从而减轻虚拟机管理程序开销。

4. 发明申请

US20130111492A1 Information Processing System, and Its Power-Saving Control Method and Device 有权
标题翻译：信息处理系统及其省电控制方法和装置
公开(公告)号：US20130111492A1
公开(公告)日：2013-05-02
申请号：US13548536
申请日：2012-07-13
申请人： Tohru Nojiri , Jun Okitsu , Yuki Kuroda , Eiichi Suzuki , Takeshi Kato , Tatsuya Saito
发明人： Tohru Nojiri , Jun Okitsu , Yuki Kuroda , Eiichi Suzuki , Takeshi Kato , Tatsuya Saito
IPC分类号： G06F9/50
CPC分类号： G06F1/206 , G06F1/3203 , G06F3/0625 , G06F9/45558 , G06F9/5094 , G06F2009/4557 , G06F2009/45591 , H04L67/1008 , Y02D10/154 , Y02D10/16 , Y02D10/22
摘要： Pieces of working information on workloads, positions of the workloads, pieces of environmental information on cooling facilities, and positions of the cooling facilities are stored as arrangement information. The pieces of working information on the workloads are estimated, and allocation of tentative workloads is deduced for fear the pieces of working information may exceed the performances of a group of information processing devices. Tentative power consumptions and arrangement information resulting from the allocation of the tentative workloads, and tentative power consumptions and arrangement information necessary for the allocation of the tentative workloads are calculated. Tentative cooling powers required to control the cooling facilities are calculated. Allocation of the tentative workloads minimizing the sum total of the tentative power consumptions of the information processing devices and the tentative cooling powers of the cooling facilities is searched. Based on the searched allocation, the workloads are allocated to the information processing devices.
摘要翻译：关于工作负载的工作信息，工作负载的位置，冷却设施的环境信息以及冷却设施的位置的部分被存储为布置信息。对工作量的工作信息进行估计，推测工作量的分配是因为担心工作信息可能会超过一组信息处理设备的性能。计算由暂定工作量的分配产生的暂时功耗和排列信息，以及暂时性工作负荷分配所需的暂时功耗和排列信息。计算控制冷却设施所需的暂时冷却功率。搜索最小化信息处理设备的暂时功耗和冷却设施的暂时冷却功率的总和的暂时工作负荷的分配。基于搜索到的分配，工作量被分配给信息处理设备。

5. 发明申请

US20110161644A1 INFORMATION PROCESSOR 审中-公开
标题翻译：信息处理器
公开(公告)号：US20110161644A1
公开(公告)日：2011-06-30
申请号：US12676600
申请日：2009-02-26
申请人： Tohru Nojiri , Keisuke Toyama , Yoshiko Nagasaka , Yuji Saeki
发明人： Tohru Nojiri , Keisuke Toyama , Yoshiko Nagasaka , Yuji Saeki
IPC分类号： G06F9/06
CPC分类号： G06F9/5077 , G06F9/5016 , G06F9/544
摘要： When a plurality of OSs are mounted, it is desirable to efficiently use memory resources without affecting other OSs. Also, even if the OSs are different from each other, they are mounted on one system, and therefore, inter-OS communication is required. In this case, data communication without affecting other OSs is required. Accordingly, an information processor includes: a firmware for assigning a first central processing unit, a first operating system, and a first region being a partial region of a memory as a first domain, assigning a second central processing unit, a second operating system, and a second region being a partial region of the memory as a second domain, and controlling to disable an access of one domain to a region assigned for the other domain; and a middleware for controlling a communication when the data communication is required between the first domain and the second domain. Further, when a sharable code is available in the operating systems, the code is stored in a region of the memory to which only a read access of each domain is enabled. Still further, when the communication is executed between the domains, with a state that the access to the memory region for the communication is limited by the middleware and the firmware, each domain accesses the region.
摘要翻译：当安装多个OS时，期望有效地使用存储器资源而不影响其他OS。此外，即使OS彼此不同，它们被安装在一个系统上，因此需要OS之间的通信。在这种情况下，需要不影响其他操作系统的数据通信。因此，信息处理器包括：用于分配第一中央处理单元，第一操作系统和作为第一域的存储器的部分区域的第一区域的固件，分配第二中央处理单元，第二操作系统，并且第二区域是作为第二域的存储器的部分区域，并且控制禁止一个域到分配给另一个域的区域的访问; 以及用于在第一域和第二域之间需要数据通信时控制通信的中间件。此外，当在操作系统中可用的代码可用时，代码被存储在只有每个域的读取访问被启用的存储器的区域中。此外，当在域之间执行通信时，具有对通信的存储区域的访问受到中间件和固件的限制的状态，每个域访问该区域。

6. 发明授权

US5065353A Adder control method and adder control circuit 失效
标题翻译： ADDER控制方法和ADDER控制电路
公开(公告)号：US5065353A
公开(公告)日：1991-11-12
申请号：US500467
申请日：1990-03-28
申请人： Tohru Nojiri , Masahiro Kainaga
发明人： Tohru Nojiri , Masahiro Kainaga
IPC分类号： G06F7/50 , G06F7/506
CPC分类号： G06F7/506 , G06F7/5052
摘要： In an adder control circuit, a plurality of full adders are so arranged that a carry bit of the full adder for calculating low orders of values to be added is inputted to the full adder for calculating high orders thereof. In this case, the addresses are controlled in response to a clock having a time period which is more than a maximum calculation time period among calculation time periods by the respective full adders required for outputting the carry bits, and is less than a total calculation time period of all full adders.

7. 发明申请

US20070286309A1 Digital broadcast receiving device and controlling method for the same 审中-公开
标题翻译：数字广播接收装置及其控制方法
公开(公告)号：US20070286309A1
公开(公告)日：2007-12-13
申请号：US11723187
申请日：2007-03-16
申请人： Tomohiko Shigeoka , Tohru Nojiri , Takehiko Nagano
发明人： Tomohiko Shigeoka , Tohru Nojiri , Takehiko Nagano
IPC分类号： H03K9/00
CPC分类号： H04N7/17318 , H04N21/435 , H04N21/4586
摘要： A digital broadcast receiving device comprises a receiving part for receiving a digital broadcast signal including first identifying information and a control part, and the control part compares the first identifying information included in the digital broadcast signal received at the receiving part and second information included in the digital broadcast receiving device, and limits or stops at least one of a plurality of functions included in the digital broadcast receiving device based on the comparison. That prevents the digital broadcast receiving device with a troubled software program being used as it is.
摘要翻译：数字广播接收装置包括：接收部件，用于接收包括第一识别信息和控制部分的数字广播信号，并且控制部分将包括在接收部分接收的数字广播信号中的第一识别信息与包含在接收部分中的第二信息进行比较数字广播接收装置，并且基于该比较限制或停止包括在数字广播接收装置中的多个功能中的至少一个功能。这样可以防止数字广播接收设备受到困扰的软件程序的使用。

8. 发明授权

US5893143A Parallel processing unit with cache memories storing NO-OP mask bits for instructions 失效
标题翻译：并行处理单元具有高速缓存存储器，用于存储用于指令的NO-OP掩码位
公开(公告)号：US5893143A
公开(公告)日：1999-04-06
申请号：US667670
申请日：1996-06-21
申请人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
发明人： Kazuhiko Tanaka , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Yoshifumi Fujikawa , Masao Ishiguro
IPC分类号： G06F9/30 , G06F9/38 , G06F12/08
CPC分类号： G06F9/3802 , G06F12/0875 , G06F9/3885
摘要： Each processing unit 110a to 110d has an individual cache memory 100a to 100d. When the cache memories read an instruction from a main storage 5, an instruction field is distributed to the cache memories. Each cache memory is controlled by a common control circuit 20. A compiler operates to schedule the processes so as to focus the processes to be executed on a specific processing unit. According to the scheduled processes, the volumes of the cache memories 100a to 100d are specified according to each execution ratio of the corresponding processing units to the cache memories. In the foregoing arrangement, a processor provides the processing units controlled by a sole program counter and improves processing by improving the efficiency of the cache memory. Further, the processor improves the efficiency of the cache memory by deleting unnecessary codes.
摘要翻译：每个处理单元110a至110d具有单独的高速缓冲存储器100a至100d。当高速缓冲存储器读取来自主存储器5的指令时，指令字段被分配到高速缓冲存储器。每个高速缓冲存储器由公共控制电路20控制。编译器操作以调度处理，以将要执行的处理集中在特定处理单元上。根据调度处理，根据相应的处理单元与高速缓冲存储器的各个执行率来指定高速缓冲存储器100a至100d的容量。在上述布置中，处理器提供由唯一程序计数器控制的处理单元，并且通过提高高速缓冲存储器的效率来改进处理。此外，处理器通过删除不必要的代码来提高高速缓冲存储器的效率。

9. 发明授权

US5872964A Comparison operating unit and graphic operating system 失效
标题翻译：比较操作单元和图形操作系统
公开(公告)号：US5872964A
公开(公告)日：1999-02-16
申请号：US693896
申请日：1996-08-05
申请人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
发明人： Masao Ishiguro , Keiji Kojima , Kiyokazu Nishioka , Tohru Nojiri , Kazuhiko Tanaka , Yoshifumi Fujikawa
IPC分类号： G06F7/02 , G06F9/30 , G06F9/305 , G06F9/38
CPC分类号： G06F9/30021 , G06F9/3885
摘要： A unit for efficiently carrying out a comparison operation and making it possible to prevent a generation of a disturbance in a pipeline during a pipeline operation is provided. This unit includes a first storage unit for storing storage information on two data to be compared, kind of comparison operation and result of comparison operation respectively, a second storage unit for storing said two data, kind of comparison operation and result of comparison operation, an operating unit for carrying out a predetermined plurality of kinds of comparison operations for two data, a selecting unit for selecting any one of results of comparison operation, and a processing unit for carrying out a processing of a comparison operation. The processing unit checks a storage destination of two data to be compared, gives the two data to the operating unit, checks a storage destination of a kind of a comparison operation, controls the selecting unit to select a result of an operation corresponding to the kind of comparison operation, and stores the operation result into a storage destination in the second storage unit.
摘要翻译：提供一种用于有效地执行比较操作并且可以防止在管道操作期间在管道中产生干扰的单元。该单元包括：第一存储单元，用于存储关于要比较的两个数据的存储信息，比较操作的种类和比较操作的结果;用于存储所述两个数据的第二存储单元，比较操作的种类和比较操作的结果; 操作单元，用于对两个数据执行预定的多种比较操作;选择单元，用于选择比较结果的任一个;以及处理单元，用于执行比较操作的处理。处理单元检查要比较的两个数据的存储目的地，将两个数据给予操作单元，检查比较操作的种类的存储目的地，控制选择单元选择与该种类对应的操作的结果并将运算结果存储在第二存储单元中的存储目的地。

10. 发明授权

US5517664A RISC system with instructions which include register area and displacement portions for accessing data stored in registers during processing 失效
标题翻译：具有指令的RISC系统，其包括用于在处理期间访问存储在寄存器中的数据的寄存器区域和位移部分
公开(公告)号：US5517664A
公开(公告)日：1996-05-14
申请号：US459965
申请日：1995-06-02
申请人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
发明人： Tan Watanabe , Keiichi Kurakazu , Yugo Kashiwagi , Keisuke Toyama , Tohru Nojiri
IPC分类号： G06F15/00 , G06F9/30 , G06F9/318 , G06F9/355 , G06F9/40 , G06F9/42 , G06F9/46 , G06F9/48 , G06F12/00 , G06F12/02
CPC分类号： G06F9/30138 , G06F9/30105 , G06F9/30127 , G06F9/30134 , G06F9/342 , G06F9/4425 , G06F9/461 , G06F9/462
摘要： In a computer system equipped with a large number of registers which have an access time much shorter than that of a main memory, a register designating address part in which the assignment of an area register having a register address of a register area as its value and the assignment of a register displacement value expressing a relative register address within the register area are combined is provided in each instruction so that, even when physical registers are increased, save and restore of registers attendant upon task switches, etc. may be lessened to attain a raised speed of program run processing.Besides, an address part for designating the main memory is provided in the same instruction.
摘要翻译：在配备有大量寄存器的计算机系统中，其存取时间比主存储器短得多;寄存器指定地址部分，其中具有寄存器区域的寄存器地址的区域寄存器的分配作为其值，以及在每个指令中提供了表示寄存器区域内的相对寄存器地址的寄存器位移值的分配，使得即使当物理寄存器增加时，也可以减少对任务切换等等的寄存器的保存和恢复以达到程序运行处理速度提高。此外，在相同的指令中提供了用于指定主存储器的地址部分。

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