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1. 发明申请

US20120117413A1 METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs) 失效
标题翻译：方法和基础设施，用于在协调的现场可编程门阵列（FPGA）上的大规模数字电路上进行循环复制仿真
公开(公告)号：US20120117413A1
公开(公告)日：2012-05-10
申请号：US12941834
申请日：2010-11-08
申请人： Sameh W. Asaad , Ralph E. Bellofatto , Bernard Brezzo , Charles L. Haymes , Mohit Kapur , Benjamin D. Parker , Thomas Roewer , Jose A. Tierno
发明人： Sameh W. Asaad , Ralph E. Bellofatto , Bernard Brezzo , Charles L. Haymes , Mohit Kapur , Benjamin D. Parker , Thomas Roewer , Jose A. Tierno
IPC分类号： G06F1/06 , G06F1/04
CPC分类号： G06F1/10 , G06F1/06 , G06F17/5027 , H03K19/17736
摘要： A plurality of target field programmable gate arrays are interconnected in accordance with a connection topology and map portions of a target system. A control module is coupled to the plurality of target field programmable gate arrays. A balanced clock distribution network is configured to distribute a reference clock signal, and a balanced reset distribution network is coupled to the control module and configured to distribute a reset signal to the plurality of target field programmable gate arrays. The control module and the balanced reset distribution network are cooperatively configured to initiate and control a simulation of the target system with the plurality of target field programmable gate arrays. A plurality of local clock control state machines reside in the target field programmable gate arrays. The local clock control state machines are coupled to the balanced clock distribution network and obtain the reference clock signal therefrom. The plurality of local clock control state machines are configured to generate a set of synchronized free-running and stoppable clocks to maintain cycle-accurate and cycle-reproducible execution of the simulation of the target system. A method is also provided.
摘要翻译：多个目标现场可编程门阵列根据目标系统的连接拓扑和地图部分互连。控制模块耦合到多个目标现场可编程门阵列。平衡时钟分配网络被配置为分配参考时钟信号，并且平衡复位分配网络耦合到控制模块并且被配置为将复位信号分配给多个目标现场可编程门阵列。控制模块和平衡复位分配网络协同配置以启动和控制目标系统与多个目标现场可编程门阵列的模拟。多个本地时钟控制状态机驻留在目标现场可编程门阵列中。本地时钟控制状态机耦合到平衡时钟分配网络并从其获得参考时钟信号。多个本地时钟控制状态机被配置为生成一组同步的自由运行和可停止时钟，以维持目标系统的模拟的循环精确和循环可再现的执行。还提供了一种方法。

2. 发明授权

US08375269B2 Data transmission system and method of correcting an error in parallel data paths of a data transmission system 失效
标题翻译：数据传输系统及数据传输系统并行数据路径中的错误校正方法
公开(公告)号：US08375269B2
公开(公告)日：2013-02-12
申请号：US12024078
申请日：2008-01-31
申请人： Charles L. Haymes , Jose A. Tierno
发明人： Charles L. Haymes , Jose A. Tierno
IPC分类号： H03M13/00 , H03M13/19
CPC分类号： H04L1/0042 , H03M5/06 , H03M13/19 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L25/03146 , H04L25/4908
摘要： A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths.
摘要翻译：数据传输系统包括用于发送数据的并行数据路径，以及编码器，用于对数据进行编码，使得针对跨并行数据路径的相同比特位置的数据生成纠错码。

3. 发明授权

US07509568B2 Error type identification circuit for identifying different types of errors in communications devices 失效
标题翻译：用于识别通信设备中不同类型错误的错误类型识别电路
公开(公告)号：US07509568B2
公开(公告)日：2009-03-24
申请号：US11033077
申请日：2005-01-11
申请人： Mohit Kapur , Jose A. Tierno
发明人： Mohit Kapur , Jose A. Tierno
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： An apparatus, method, and computer program product to identify types of errors that occur in a communications device under test and where only the presence of an error is indicated by an error checker. Each presence of an error bit in an error signal during a first period of time output from the error data checker is identified. The error bit indicates only that a mismatch occurred between an input signal input into the device and an output signal output from the device. The error bit is generated in response to an error in the device under test. The error bit includes no information about a type of the error. The type of the error is determined by determining a number of occurrences of the error bit in the error signal during the first period of time.
摘要翻译：一种用于识别发生在被测通信设备中的错误类型的装置，方法和计算机程序产品，并且其中只有错误检查器指示错误的存在。识别在从错误数据检查器输出的第一时间周期内存在错误信号中的错误位的每一个。误差位仅指示输入到器件的输入信号与从器件输出的输出信号之间发生不匹配。响应于被测设备中的错误而产生错误位。错误位不包含有关错误类型的信息。误差的类型通过确定在第一时间段期间误差信号中出现的错误位数来确定。

4. 发明申请

US20090199070A1 DATA TRANSMISSION SYSTEM AND METHOD OF CORRECTING AN ERROR IN PARALLEL DATA PATHS OF A DATA TRANSMISSION SYSTEM 失效
标题翻译：数据传输系统和校正数据传输系统并行数据的错误的方法
公开(公告)号：US20090199070A1
公开(公告)日：2009-08-06
申请号：US12024078
申请日：2008-01-31
申请人： Charles L. Haymes , Jose A. Tierno
发明人： Charles L. Haymes , Jose A. Tierno
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H04L1/0042 , H03M5/06 , H03M13/19 , H04L1/0057 , H04L1/0065 , H04L1/0071 , H04L25/03146 , H04L25/4908
摘要： A data transmission system includes parallel data paths for transmitting data, and an encoder for encoding the data such that an error correction code is generated for data at a same bit position across the parallel data paths.
摘要翻译：数据传输系统包括用于发送数据的并行数据路径，以及编码器，用于对数据进行编码，使得针对跨并行数据路径的相同比特位置的数据生成纠错码。

5. 发明授权

US07602869B2 Methods and apparatus for clock synchronization and data recovery in a receiver 有权
标题翻译：接收机中时钟同步和数据恢复的方法和装置
公开(公告)号：US07602869B2
公开(公告)日：2009-10-13
申请号：US11193868
申请日：2005-07-29
申请人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
发明人： Azita Emami-Neyestanak , Mounir Meghelli , Benjamin D. Parker , Sergey V. Rylov , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H04L7/00
CPC分类号： H04L7/0337
摘要： Clock synchronization and data recovery techniques are disclosed. For example, a technique for synchronizing a clock for use in recovering received data comprises the following steps/operations. A first clock (e.g., a data clock) is set for a first sampling cycle to a first phase position within a given unit interval in the received data. A second clock (e.g., a sweep clock) is swept through other phase positions with respect to the first phase position such that a transition from the given unit interval to another unit interval in the received data is determined. A sampling point is determined based on measurements at the phase positions associated with the second clock. The second clock is set to the phase position corresponding to the sampling point such that data may be recovered at that sampling point. Further, for a next sampling cycle, the first clock may be used to sweep through phase positions with respect to the set phase position of the second clock corresponding to the sampling point in the first sampling cycle such that a next sampling point may be determined.
摘要翻译：公开了时钟同步和数据恢复技术。例如，用于同步用于恢复接收到的数据的时钟的技术包括以下步骤/操作。将第一时钟（例如，数据时钟）设置为在接收到的数据中的给定单位间隔内的第一相位位置的第一采样周期。第二时钟（例如，扫描时钟）相对于第一相位位置扫过其它相位位置，从而确定从接收到的数据中的给定单位间隔到另一个单位间隔的转变。基于与第二时钟相关联的相位位置处的测量来确定采样点。将第二时钟设置为对应于采样点的相位位置，使得可以在该采样点恢复数据。此外，对于下一采样周期，可以使用第一时钟相对于与第一采样周期中的采样点对应的第二时钟的设置相位位置扫描相位位置，使得可以确定下一采样点。

6. 发明授权

US09157950B2 Loop parameter sensor using repetitive phase errors 有权
标题翻译：循环参数传感器使用重复相位误差
公开(公告)号：US09157950B2
公开(公告)日：2015-10-13
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00 , G01R31/28 , H03L7/093 , H03L7/107 , H03L7/18
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译：公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。在一个实施例中，该参数被计算为交叉时间的数学函数。该参数可以是例如PLL的带宽。

7. 发明申请

US20120262149A1 LOOP PARAMETER SENSOR USING REPETITIVE PHASE ERRORS 有权
标题翻译：使用重复相位错误的环路参数传感器
公开(公告)号：US20120262149A1
公开(公告)日：2012-10-18
申请号：US13088949
申请日：2011-04-18
申请人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
发明人： Mark Ferriss , Arun S. Natarajan , Benjamin D. Parker , Alexander V. Rylyakov , Jose A. Tierno , Soner Yaldiz
IPC分类号： G01R25/00
CPC分类号： H03L7/085 , G01R31/2824 , H03L7/093 , H03L7/1075 , H03L7/1077 , H03L7/18 , H03L2207/06
摘要： A method and system are disclosed for measuring a specified parameter in a phase-locked loop frequency synthesizer (PLL). In one embodiment, the method comprises introducing multiple phase errors in the PLL, measuring a specified aspect of the introduced phase errors, and determining a value for the specified parameter using the measured aspects of the introduced phase errors. In one embodiment, the phase errors are introduced repetitively in the PLL, and these phase errors produce a modified phase difference between the reference signal and the feedback signal in the PPL. In one embodiment, crossover times, when this modified phase difference crosses over a preset value, are determined, and these crossover times are used to determine the value for the specified parameter. In an embodiment, the parameter is calculated as a mathematical function of the crossover times. The parameter may be, for example, the bandwidth of the PLL.
摘要翻译：公开了用于测量锁相环频率合成器（PLL）中的指定参数的方法和系统。在一个实施例中，该方法包括在PLL中引入多个相位误差，测量所引入的相位误差的特定方面，以及使用引入的相位误差的测量方面来确定所述指定参数的值。在一个实施例中，在PLL中重复地引入相位误差，并且这些相位误差在PPL中产生参考信号和反馈信号之间的修正的相位差。在一个实施例中，当修改的相位差超过预设值时，交叉时间被确定，并且这些交叉时间被用于确定指定参数的值。在一个实施例中，该参数被计算为交叉时间的数学函数。该参数可以是例如PLL的带宽。

8. 发明申请

US20130076449A1 VARACTOR TUNING CONTROL USING REDUNDANT NUMBERING 失效
标题翻译：使用冗余编号的变频调速控制
公开(公告)号：US20130076449A1
公开(公告)日：2013-03-28
申请号：US13245409
申请日：2011-09-26
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03L2207/50
摘要： Techniques for improved tuning control of varactor circuits are disclosed. For example, an apparatus comprises a plurality of varactors for tuning a frequency value. The plurality of varactors comprises approximately sqrt(2N) varactors, where N is a number of tunings steps and the plurality of varactors are respectively sized as 1x, 2x, 3x, 4x, . . . , approximately sqrt(2N)x, and where x is a unit of capacitance. A given one of the N tuning steps may be represented by more than one combination of varactors. This may be referred to as redundant numbering.
摘要翻译：公开了用于改进变容二极管电路调谐控制的技术。例如，一种装置包括用于调谐频率值的多个变容二极管。多个变容二极管包括大约sqrt（2N）变容二极管，其中N是调谐步骤的数量，并且多个变容二极管分别尺寸为1x，2x，3x，4x。。。，约为sqrt（2N）x，其中x为电容单位。 N个调谐步骤中的给定一个可以由多个组合的变容二极管表示。这可以称为冗余编号。

9. 发明授权

US08264285B2 Method and apparatus for low latency proportional path in a digitally controlled system 有权
标题翻译：数字控制系统中低延迟比例路径的方法和装置
公开(公告)号：US08264285B2
公开(公告)日：2012-09-11
申请号：US12175012
申请日：2008-07-17
申请人： Alexander V. Rylyakov , Jose A. Tierno
发明人： Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/00
CPC分类号： H03L7/10 , H03L7/093 , H03L7/099 , H03L2207/06
摘要： A digitally controlled circuit and method includes an error input coupled to a proportional path. The proportional path includes a selector which directly receives the error input as a select signal. The selector receives a proportional control weight from a location other than the proportional path wherein the proportional control weight is input to a digitally controlled oscillator (DCO).
摘要翻译：数字控制电路和方法包括耦合到比例路径的误差输入。比例路径包括直接接收误差输入作为选择信号的选择器。选择器从比例路径（其中比例控制权重被输入到数字控制振荡器（DCO））以外的位置接收比例控制权重。

10. 发明授权

US07772900B2 Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators 失效
标题翻译：锁相环电路和实现脉冲宽度调制的方法，用于数字控制振荡器的微调控制
公开(公告)号：US07772900B2
公开(公告)日：2010-08-10
申请号：US12173140
申请日：2008-07-15
申请人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
发明人： Herschel A. Ainspan , Daniel J. Friedman , Alexander V. Rylyakov , Jose A. Tierno
IPC分类号： H03L7/06
CPC分类号： H03L7/107 , H03L7/093 , H03L7/1075 , H03L2207/50
摘要： PLL (phase locked loop) circuits and methods are provided in which PWM (pulse width modulation) techniques are to achieve continuous fine tuning control of DCO (digitally controlled oscillator) circuits. In general, pulse width modulation techniques are applied to further modulate dithered control signals that are used to enhance the frequency tuning resolution of the DCO such that the dithered control signals are applied to the fractional tracking control port of the DCO for a selected fraction of a full clock signal based pulse width modulation applied.
摘要翻译：提供PLL（锁相环）电路和方法，其中PWM（脉宽调制）技术将实现DCO（数字控制振荡器）电路的连续微调控制。通常，应用脉冲宽度调制技术来进一步调制用于增强DCO的频率调谐分辨率的抖动控制信号，使得抖动控制信号被施加到DCO的分数跟踪控制端口，用于所选择的部分采用全时钟信号脉冲宽度调制。

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