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1. 发明授权

US5034908A Digit-serial transversal filters 失效
标题翻译：数字串行横向滤波器
公开(公告)号：US5034908A
公开(公告)日：1991-07-23
申请号：US504503
申请日：1990-04-02
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00
摘要： One type of transversal filter using digit-serial signals in its operation comprises a to-digit-serial converter for converting a succession of input data words received at its input port each to a respective succession of m-bit-wide digits supplied from its output port in order of progressively greater significance, m being a positive plural integer; a clocked delay line having an input tap connected for responding to the m-bit-wide digits supplied from the output port of the to-digit-serial converter and having at least one further tap for supplying a respective tap signal; and means for performing a weighted summation of the input signal to the clocked delay line and each tap signal from the clocked delay line, to generate a filter response in digit-serial format. Another type of transversal filter, which uses digit-serial signals in its operation, comprises a plurality, p in number, of parallel-to-digit-serial converters, each for generating a respective m-bit-wide digit-serial data stream by converting n-parallel-bit words in an input signal to the digital filter, m being a positive integer and n being the product of m and p; a plurality of tapped delay lines having respective input taps connected from respective ones of said parallel-to-digit-serial converters and each having at least one further tap; means for generating p different phases of filter response in digit-serial form by weighting and summing digital signals taken from respective taps on ones of the p tapped delay lines; and p digit-serial-to-parallel converters for converting, on a cyclic basis, the different phases of filter response to parallel-bit words in an output signal from the digital filter.
摘要翻译：在其操作中使用数字串行信号的一种类型的横向滤波器包括一个数字串行转换器，用于将在其输入端口处接收的一系列输入数据字转换成从其输出端提供的各个相继的m位宽数字端口按顺序逐渐显现，m为正整数; 时钟延迟线具有连接的输入抽头，用于响应从位数字串行转换器的输出端口提供的m位宽数字，并具有用于提供相应抽头信号的至少一个另外的抽头; 以及用于对来自时钟延迟线的时钟延迟线和每个抽头信号执行输入信号的加权求和的装置，以产生数字串行格式的滤波器响应。在其操作中使用数字串行信号的另一种类型的横向滤波器包括多个并行数字串行转换器，每个转换器用于通过以下步骤产生相应的m位宽数字串行数据流：将输入信号中的n个并行位字转换为数字滤波器，m是正整数，n是m和p的乘积; 多个抽头延迟线，其具有从相应的所述并行到数字串行转换器连接的各个输入抽头，并且每个具有至少一个另外的抽头; 用于以数字串行形式产生滤波器响应的p个不同相位的装置，用于通过对从所述p个抽头延迟线中的一个上的各个抽头获得的数字信号进行加权和求和; 和p位串行到并行转换器，用于在来自数字滤波器的输出信号中循环地将滤波器响应的不同相位转换成并行位字。

2. 发明授权

US5164724A Data format converters for use with digit-serial signals 失效
标题翻译：用于数字串行信号的数据格式转换器
公开(公告)号：US5164724A
公开(公告)日：1992-11-17
申请号：US553914
申请日：1990-07-16
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00 , G06F2207/386 , G06F2207/3896
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.
摘要翻译：转换装置用于将数字数据字转换为数字串行数据格式，其中数字位宽对于数字数据字的后续处理是最佳的。关于吞吐量效率的优化是与集成电路的吞吐率成比例的集成电路性能的量度，并且与集成电路的面积成反比，其包括处理电路和伴随的转换电路。

3. 发明授权

US4942396A To-digit-serial converters for systems processing data in digit-serial format 失效
标题翻译：用于以数字串行格式处理数据的系统的数位串行转换器
公开(公告)号：US4942396A
公开(公告)日：1990-07-17
申请号：US347860
申请日：1989-05-04
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa , Sharbel E. Noujaim
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00 , G06F2207/386 , G06F2207/3896
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.
摘要翻译：转换装置用于将数字数据字转换为数字串行数据格式，其中数字位宽对于数字数据字的后续处理是最佳的。关于吞吐量效率的优化是与集成电路的吞吐率成比例的集成电路性能的量度，并且与集成电路的面积成反比，其包括处理电路和伴随的转换电路。

4. 发明授权

US5025257A Increased performance of digital integrated circuits by processing with multiple-bit-width digits 失效
公开(公告)号：US5025257A
公开(公告)日：1991-06-18
申请号：US482122
申请日：1990-02-20
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.

5. 发明授权

US5016011A Increased performance of digital integrated circuits by processing with multiple-bit-width digits 失效
标题翻译：数字集成电路通过多位数位处理提高性能
公开(公告)号：US5016011A
公开(公告)日：1991-05-14
申请号：US482121
申请日：1990-02-20
申请人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa
发明人： Richard I. Hartley , Peter F. Corbett , Fathy F. Yassa
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00
摘要： Conversion apparatus is used to convert digital data words to a digit-serial data format wherein digit bit-width is optimal for subsequent processing of the digital data words. Optimization is with regard to throughput efficiency, a measure of integrated circuit performance proportional to throughput rate of integrated circuitry and inversely proportional to the area of that integrated circuitry, comprising processing circuitry and attendant conversion circuitry.
摘要翻译：转换装置用于将数字数据字转换为数字串行数据格式，其中数字位宽对于数字数据字的后续处理是最佳的。关于吞吐量效率的优化是与集成电路的吞吐率成比例的集成电路性能的量度，并且与集成电路的面积成反比，其包括处理电路和伴随的转换电路。

6. 发明授权

US4985834A System and method employing pipelined parallel circuit architecture for displaying surface structures of the interior region of a solid body 失效
标题翻译：采用流水线并联电路架构的系统和方法，用于显示固体的内部区域的表面结构
公开(公告)号：US4985834A
公开(公告)日：1991-01-15
申请号：US275154
申请日：1988-11-22
申请人： Harvey E. Cline , Richard I. Hartley , Siegwalt Ludke , Sharbel E. Noujaim
发明人： Harvey E. Cline , Richard I. Hartley , Siegwalt Ludke , Sharbel E. Noujaim
IPC分类号： G01N9/24 , G06T1/00 , G06T1/20 , G06T7/60 , G06T11/00 , G06T17/00
CPC分类号： G06T17/00
摘要： Arbitrary interior surfaces of a three-dimensional body are displayed from a regular array of values of at least one physical property in the interior of the body. The physical property measurements may be made with systems such as computerized tomographic x-ray, or magnetic resonance imaging. Highly parallel circuits and a highly parallel architecture permit generation of surface views in real time, i.e., sufficiently fast to support ongoing procedures such as surgical operations. These parallel circuits, realizable on large scale integrated circuit chips, perform surface normal calculations, linear interpolations and signal comparisons in simultaneously operating circuit paths which are asynchronously enabled when input data appear.
摘要翻译：三维身体的任意内表面从身体内部的至少一个物理性质的规则数组中显示出来。物理性质测量可以用诸如计算机断层X射线或磁共振成像的系统进行。高度并行的电路和高度平行的架构允许实时地产生表面视图，即足够快以支持正在进行的程序，例如外科手术。这些并行电路可在大规模集成电路芯片上实现，可在同时工作的电路路径中进行表面正常计算，线性内插和信号比较，并在输入数据出现时异步启用。

7. 发明授权

US4939687A Serial-parallel multipliers using serial as well as parallel addition of partial products 失效
标题翻译：使用串行和并行添加部分产品的串行并行乘法器
公开(公告)号：US4939687A
公开(公告)日：1990-07-03
申请号：US265734
申请日：1988-11-01
申请人： Richard I. Hartley , Sharbel E. Noujaim
发明人： Richard I. Hartley , Sharbel E. Noujaim
IPC分类号： G06F7/52
CPC分类号： G06F7/5275 , G06F2207/3896
摘要： A cell module which is particularly employable in bit-serial silicon compilation methods permits the fabrication and layout of bit-serial multipliers having variable word sizes. In particular, the cell module permits the fabrication of a bit-serial multiplier which is capable of a number of different functions including the production of high-order (major) and low-order (minor) output product bit streams which may be selected from so as to provide output results in a variety of different formats associated with binary fractional multiplication.
摘要翻译：特别可用于比特串行硅编译方法的单元模块允许具有可变字大小的位串行乘法器的制造和布局。特别地，单元模块允许制造能够具有多个不同功能的位串行乘法器，包括产生高阶（主）和低阶（次）输出产品位流，其可以从以便提供与二进制分数乘法相关联的各种不同格式的输出结果。

8. 发明授权

US4860240A Low-latency two's complement bit-serial multiplier 失效
标题翻译：低延迟二进制补码位串行乘法器
公开(公告)号：US4860240A
公开(公告)日：1989-08-22
申请号：US134271
申请日：1987-12-14
申请人： Richard I. Hartley , Peter F. Corbett
发明人： Richard I. Hartley , Peter F. Corbett
IPC分类号： G06F7/52
CPC分类号： G06F7/525 , G06F2207/3896
摘要： A double precision, low-latency two's complement bit-serial multiplier operates on the fact that after both inputs have been fully read into the multiplier, the calculation has proceeded to such a stage that it may be completed with a single counter. The multiplier comprises a plurality of bit slices and an endcell connected in series. The serial bit streams of the operands are sampled by latches in each of the bit slices, and the sampled bit values are accumulated using (5,3) counters to generate partial sum output signals. The partial sum output signal for the last bit slice is the least significant word of the double precision product. The endcell comprises another (5,3) counter which accumulates propagated sum and carry output signals of the bit slices and generates the most significant word of the double precision product.
摘要翻译：双精度，低延迟二进制补码位串行乘法器的作用在于，在两个输入都被完全读入乘法器之后，计算已经进行到可以用单个计数器完成的阶段。乘法器包括串联连接的多个位片和端单元。操作数的串行比特流由每个比特片中的锁存器进行采样，并且使用（5,3）个计数器累加采样比特值以产生部分和输出信号。最后一位片段的部分和输出信号是双精度积的最低有效字。端单元包括另一个（5,3）计数器，其累积传播和并携带位片的输出信号并产生双精度乘积的最高有效字。

9. 发明授权

US5010511A Digit-serial linear combining apparatus useful in dividers 失效
标题翻译：用于分频器的数字串行线性组合装置
公开(公告)号：US5010511A
公开(公告)日：1991-04-23
申请号：US265210
申请日：1988-10-31
申请人： Richard I. Hartley , Peter F. Corbett
发明人： Richard I. Hartley , Peter F. Corbett
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Linear combining apparatus for digit-serial data performs addition, subtraction and comparison functions. The capability of performing addition or subtraction as the result of comparison permits non-restoring division to be done using a plurality of the linear combining apparatuses.
摘要翻译：数字串行数据线性组合装置执行加，减和比较功能。作为比较结果执行加法或减法的能力允许使用多个线性组合装置进行非恢复划分。

10. 发明授权

US4910700A Bit-sliced digit-serial multiplier 失效
标题翻译：位片数字串行乘法器
公开(公告)号：US4910700A
公开(公告)日：1990-03-20
申请号：US358277
申请日：1989-05-30
申请人： Richard I. Hartley , Peter F. Corbett
发明人： Richard I. Hartley , Peter F. Corbett
IPC分类号： G06F7/52 , H03M9/00
CPC分类号： G06F7/5312 , H03M9/00 , G06F2207/386 , G06F2207/3896
摘要： A digital multiplier for multiplying together W-bit digit-serial multiplier and multiplicand signals includes a combinational array of multiplier cells arranged in N rows and W columns. A digit-serial-in/parallel-out register supplies respective bits of each successive multiplicand signal to the W columns of the array, the N rows of which receive respective bits of each successive digit of the multiplier signal. After each earlier digit of the multiplier is processed, the carry and sum bits are forwarded without column shift and with one column shift, respectively, from the final row to the first row of multiplier cells. This scrolls the operation of the W-column-by-N-row multiplier cell array, allowing it to be used M times for each word of the multiplier signal, one for each of the M digits in a W-bit word of the multiplier signal. The sum bits from the final column of multiplier cells provide the minor product output signal of the digital multiplier in digit-serial format, as each digit of the multiplier signal is processed. In processing the final digit of the multiplier, the carry and sum bits are shifted differentially by one bit place and are conveyed by shift registers to a digit-serial final adder, the full sum output of which supplies the major product output signal of the digital multiplier in digit-serial form. Supplying the minor and major product output signals in parallel permits pipelined operation of the apparatus.
摘要翻译：用于将W位数字串行乘法器和被乘数信号相乘的数字乘法器包括以N行和W列布置的乘法器单元的组合阵列。数字串行输入/并行输出寄存器将每个连续被乘数信号的相应位提供给阵列的W列，其N行接收乘法器信号的每个连续数位的相应位。在处理乘法器的每个较早的数字之后，进位和和位被分别从最后一行到第一行乘法器单元转发而不进行列移位和一列移位。这将滚动W列逐行乘法器单元阵列的操作，允许它对乘法器信号的每个字使用M次，乘数中的W位字中的每个M位一个信号。随着乘法器信号的每个数字被处理，来自乘法器单元的最后一列的和位提供数字串行格式的数字乘法器的次要乘积输出信号。在处理乘法器的最终位时，进位和和位被差分地移位一位位置，并由移位寄存器传送给数字串行最终加法器，其全和输出提供数字的主要产品输出信号数字串行形式的乘数。同时提供次要和主要产品输出信号允许设备的流水线操作。

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