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1. 发明申请

US20060271822A1 Method and system for quantifying the quality of diagnostic software 有权
标题翻译：用于量化诊断软件质量的方法和系统
公开(公告)号：US20060271822A1
公开(公告)日：2006-11-30
申请号：US11138734
申请日：2005-05-26
申请人： Rahul Pal , Kumar Vadhri , Gulam Dastagir
发明人： Rahul Pal , Kumar Vadhri , Gulam Dastagir
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a computing system. The method involves executing the diagnostic software in an Integrated Circuit (IC) verification environment. The diagnostic software is executed by a Virtual Computer-processing Unit (V-CPU), which models (Central Processing Unit) CPU of the computing system to be tested.
摘要翻译：提供了一种通过应用覆盖工具来量化诊断软件的质量的方法，系统和装置，其中诊断软件用于测试计算系统。该方法涉及在集成电路（IC）验证环境中执行诊断软件。诊断软件由要测试的计算系统的型号（中央处理单元）CPU的虚拟计算机处理单元（V-CPU）执行。

2. 发明授权

US07340386B2 Method and system for quantifying the quality of diagnostic software 有权
标题翻译：用于量化诊断软件质量的方法和系统
公开(公告)号：US07340386B2
公开(公告)日：2008-03-04
申请号：US11138734
申请日：2005-05-26
申请人： Rahul Pal , Kumar Vadhri , Gulam Dastagir
发明人： Rahul Pal , Kumar Vadhri , Gulam Dastagir
IPC分类号： G06F17/50
CPC分类号： G06F11/261
摘要： A method, a system, and an apparatus for quantification of the quality of diagnostic software by applying a coverage tool are provided, wherein the diagnostic software is used for testing a computing system. The method involves executing the diagnostic software in an Integrated Circuit (IC) verification environment. The diagnostic software is executed by a Virtual Computer-processing Unit (V-CPU), which models (Central Processing Unit) CPU of the computing system to be tested.
摘要翻译：提供了一种通过应用覆盖工具来量化诊断软件的质量的方法，系统和装置，其中诊断软件用于测试计算系统。该方法涉及在集成电路（IC）验证环境中执行诊断软件。诊断软件由要测试的计算系统的型号（中央处理单元）CPU的虚拟计算机处理单元（V-CPU）执行。

3. 发明申请

US20140359230A1 PROTOCOL FOR CONFLICTING MEMORY TRANSACTIONS 有权
标题翻译：冲突内存交易协议
公开(公告)号：US20140359230A1
公开(公告)日：2014-12-04
申请号：US13997900
申请日：2011-12-20
申请人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
发明人： Manoj K. Arora , Robert G. Blankenship , Rahul Pal , Dheemanth Nagaraj
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/0824 , G06F12/0828 , G06F12/0831 , G06F13/14 , G06F13/38
摘要： Embodiments of the invention describe a cache coherency protocol that eliminates the need for ordering between message classes and also eliminates home tracker preallocation. Embodiments of the invention describe a less complex conflict detection and resolution mechanism (at the home agent) without any performance degradation in form of bandwidth or latency compared to prior art solutions.Embodiments of the invention describe a home agent that may receive request messages, e.g., data ownership request messages and data request messages, which include issuance data indicating an order of the respective message issued. Said home agent may determine whether an early or late conflict exists based, at least in part, on a received conflict response message and the issuance data of a most recent completed transaction.
摘要翻译：本发明的实施例描述了高速缓存一致性协议，其消除了在消息类之间排序的需要，并且还消除了家庭跟踪器预分配。与现有技术的解决方案相比，本发明的实施例描述了一种不太复杂的冲突检测和解决机制（在归属代理），与带宽或延迟形式没有任何性能下降。本发明的实施例描述了可以接收诸如数据所有权请求消息和数据请求消息的请求消息的归属代理，其包括指示所发出的各个消息的顺序的发布数据。所述归属代理可以至少部分地基于接收到的冲突响应消息和最近完成的交易的发行数据来确定是否存在早期或晚期冲突。

4. 发明授权

US08862828B2 Sub-numa clustering 有权
标题翻译：亚类聚类
公开(公告)号：US08862828B2
公开(公告)日：2014-10-14
申请号：US13584656
申请日：2012-08-13
申请人： Ravindra P. Saraf , Rahul Pal , Ashok Jagannathan
发明人： Ravindra P. Saraf , Rahul Pal , Ashok Jagannathan
IPC分类号： G06F12/08
CPC分类号： G06F12/0692
摘要： Method and apparatus to efficiently store and cache data. Cores of a processor and cache slices co-located with the cores may be grouped into a cluster. A memory space may be partitioned into address regions. The cluster may be associated with an address region from the address regions. Each memory address of the address region may be mapped to one or more of the cache slices grouped into the cluster. A cache access from one or more of the cores grouped into the cluster may be biased to the address region based on the association of the cluster with the address region.
摘要翻译：有效存储和缓存数据的方法和装置。处理器的核心和与核心共处的缓存片段可以被分组成一个群集。存储器空间可以被分割成地址区域。集群可以与地址区域的地址区域相关联。可以将地址区域的每个存储器地址映射到分组到集群中的一个或多个高速缓存片段。基于群集与地址区域的关联，可以将分组到群集中的一个或多个核心的高速缓存访问偏移到地址区域。

5. 发明申请

US20120131282A1 Providing A Directory Cache For Peripheral Devices 失效
标题翻译：为外围设备提供目录缓存
公开(公告)号：US20120131282A1
公开(公告)日：2012-05-24
申请号：US12953120
申请日：2010-11-23
申请人： Andrew Y. Sun , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Ravindra P. Saraf
发明人： Andrew Y. Sun , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Ravindra P. Saraf
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： In one embodiment, the present invention includes a processor having at least one core and uncore logic. The uncore logic can include a home agent to act as a guard to control access to a memory region. Either in the home agent or another portion of the uncore logic, a directory cache may be provided to store ownership information for a portion of the memory region owned by an agent coupled to the processor. In this way, when an access request for the memory region misses in the directory cache, a memory transaction can be avoided. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有至少一个核和非逻辑逻辑的处理器。非逻辑逻辑可以包括用作控制对存储器区域的访问的保护的归属代理。在归属代理或非逻辑逻辑的另一部分中，可以提供目录高速缓存以存储由耦合到处理器的代理拥有的存储器区域的一部分的所有权信息。以这种方式，当存储器区域的访问请求在目录高速缓存中丢失时，可以避免存储器事务。描述和要求保护其他实施例。

6. 发明公开

US20240354248A1 DATA TRANSFER USING COHERENT DOORBELL UPDATES 审中-公开
公开(公告)号：US20240354248A1
公开(公告)日：2024-10-24
申请号：US18756818
申请日：2024-06-27
申请人： Rahul Pal , Ashish Gupta , Randy Bright , Yoanna Baumgartner
发明人： Rahul Pal , Ashish Gupta , Randy Bright , Yoanna Baumgartner
IPC分类号： G06F12/0804 , G06F13/16
CPC分类号： G06F12/0804 , G06F13/1668 , G06F2213/0026
摘要： Systems or methods of the present disclosure may provide systems and techniques for efficiently transferring data between a host processing unit and connected devices using coherent doorbell register updates. For example, a method may include: receiving, via controller of host processing circuitry, an attempt to write data to a cacheable memory address from a processing unit of the host processing circuitry; transmitting, via the controller, an indication of the attempt to write to the cacheable memory address to a device; receiving, via the controller, an acknowledgment from the device that the cacheable memory address has been deallocated by the device; and writing, via the controller, the data to the cacheable memory address in response to the acknowledgement from the device.

7. 发明申请

US20230027807A1 Method and Apparatus to Enable CPU Host-Unaware Dynamic FPGA Reconfiguration 有权
公开(公告)号：US20230027807A1
公开(公告)日：2023-01-26
申请号：US17956555
申请日：2022-09-29
申请人： Rahul Pal , Ashish Gupta , Gary Wallichs , Sreedhar Ravipalli
发明人： Rahul Pal , Ashish Gupta , Gary Wallichs , Sreedhar Ravipalli
IPC分类号： G06F30/343 , G06F13/10 , G06F13/16 , H03K19/17728
摘要： The present disclosure is directed to enabling operation of a field programmable gate array (FPGA) while preventing application quiescence during FPGA reconfiguration. In embodiments of the disclosure, proxy agent firmware may enable downstream transactions (e.g., PCIe transactions) to be serviced during reconfiguration of the FPGA. Programmable logic states (e.g., PCIe configuration states or memory-mapped input/output (MMIO) states) are saved in memory and maintained by the proxy agent (via a management controller running the proxy agent). Once the FPGA is reconfigured, the state may be restored to the FPGA's programmable logic, and the FPGA may operate on the current state of the transactions.

8. 发明申请

US20120047333A1 EXTENDING A CACHE COHERENCY SNOOP BROADCAST PROTOCOL WITH DIRECTORY INFORMATION 失效
标题翻译：扩展带有目录信息的高速缓存的SNOOP广播协议
公开(公告)号：US20120047333A1
公开(公告)日：2012-02-23
申请号：US12860340
申请日：2010-08-20
申请人： SAILESH KOTTAPALLI , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Dheemanth Nagaraj
发明人： SAILESH KOTTAPALLI , Henk G. Neefs , Rahul Pal , Manoj K. Arora , Dheemanth Nagaraj
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0833 , G06F12/0817 , G06F12/0822 , G06F12/0831 , G06F12/084 , G06F13/4265 , G06F2212/621 , G06F2212/622
摘要： In one embodiment, a method includes receiving a read request from a first caching agent, determining whether a directory entry associated with the memory location indicates that the information is not present in a remote caching agent, and if so, transmitting the information from the memory location to the first caching agent before snoop processing with respect to the read request is completed. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种方法包括从第一高速缓存代理接收读取请求，确定与存储器位置相关联的目录条目是否指示该信息不存在于远程高速缓存代理中，如果是，则将该信息从存储器关于读取请求的窥探处理之前的第一高速缓存代理的位置被完成。描述和要求保护其他实施例。

9. 发明公开

US20240345884A1 IC Device Resource Sharing 审中-公开
公开(公告)号：US20240345884A1
公开(公告)日：2024-10-17
申请号：US18756964
申请日：2024-06-27
申请人： Ashish Gupta , Rahul Pal , Zhi-Hern Loh , Keong Hong Oh , Thuyet Gia Ngo
发明人： Ashish Gupta , Rahul Pal , Zhi-Hern Loh , Keong Hong Oh , Thuyet Gia Ngo
IPC分类号： G06F9/50
CPC分类号： G06F9/5027
摘要： Systems or methods of the present disclosure may provide systems and techniques for sharing resources of an IC device between communications pipelines of the IC device. For example, a method may include: receiving a request from a first initiator component, the request associated with a first communication protocol; storing the request in a shared buffer; receiving a response from a first target component, the response associated with a second communication protocol; storing the response in the shared buffer; sending the request from the shared buffer to a second target component; and sending the response from the shared buffer to a second initiator component.

10. 发明申请

US20220405453A1 SYSTEMS AND METHODS FOR REDUCING CONGESTION ON NETWORK-ON-CHIP 有权
公开(公告)号：US20220405453A1
公开(公告)日：2022-12-22
申请号：US17854341
申请日：2022-06-30
申请人： Rahul Pal , Ashish Gupta , Navid Azizi , Jeffrey Schulz , Yin Chong Hew , Thuyet Ngo , George Chong Hean Ooi , Vikrant Kapila , Kok Kee Looi
发明人： Rahul Pal , Ashish Gupta , Navid Azizi , Jeffrey Schulz , Yin Chong Hew , Thuyet Ngo , George Chong Hean Ooi , Vikrant Kapila , Kok Kee Looi
IPC分类号： G06F30/34 , G06F9/54 , G06F9/30
摘要： Systems or methods of the present disclosure may provide a programmable logic device including a network-on-chip (NoC) to facilitate data transfer between one or more main intellectual property components (main IP) and one or more secondary intellectual property components (secondary IP). To reduce or prevent excessive congestion on the NoC, the NoC may include one or more traffic throttlers that may receive feedback from a data buffer, a main bridge, or both and adjust data injection rate based on the feedback. Additionally, the NoC may include a data mapper to enable data transfer to be remapped from a first destination to a second destination if congestion is detected at the first destination.

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