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1. 发明授权

US06620560B2 Plasma treatment of low-k dielectric films to improve patterning 有权
公开(公告)号：US06620560B2
公开(公告)日：2003-09-16
申请号：US09975109
申请日：2001-10-11
申请人： Ping Jiang , Guoqiang Xing , Andrew J. McKerrow , Robert Kraft , Hyesook Hong
发明人： Ping Jiang , Guoqiang Xing , Andrew J. McKerrow , Robert Kraft , Hyesook Hong
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/31116 , H01L21/31138 , H01L21/76808 , H01L21/76826
摘要： Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The plasma treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130, 132), during a rework of the pattern (130, 132), or between via and trench patterning to reduce resist poisoning.

2. 发明授权

US07129162B2 Dual cap layer in damascene interconnection processes 有权
标题翻译：大马士革互连工艺中的双盖层
公开(公告)号：US07129162B2
公开(公告)日：2006-10-31
申请号：US10429119
申请日：2003-05-02
申请人： Hyesook Hong , Guoqiang Xing , Ping Jiang
发明人： Hyesook Hong , Guoqiang Xing , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76832 , H01L21/76801 , H01L21/76802 , H01L21/76808
摘要： Damascene methods for forming copper conductors (30, 130) are disclosed. According to the disclosed method, a dual cap layer (18, 20; 122, 124) is formed over an organosilicate glass insulating layer (16; 116, 120) prior to the etching of a via or trench toward an underlying conductor (12; 112). The dual cap layer includes a layer of silicon carbide (18; 124) and a layer of silicon nitride (20; 122). The silicon carbide layer (18; 124) and silicon nitride layer (20; 122) can be deposited in either order relative to one another. The silicon carbide layer (18; 124) maintains the critical dimension of the via or trench as it is etched through the insulating layer (16; 116, 120), while the silicon nitride layer (20; 122) inhibits the failure mechanism of resist poisoning. The method is applicable to single damascene processes, but may also be used in dual damascene copper processes.
摘要翻译：公开了用于形成铜导体（30,130）的镶嵌方法。根据所公开的方法，在将通孔或沟槽蚀刻到下面的导体（12;）之前，在有机硅酸盐玻璃绝缘层（16; 116,120）上形成双重覆盖层（18,20; 122,124）。 112）。双盖层包括碳化硅层（18; 124）和氮化硅层（20; 122）。碳化硅层（18; 124）和氮化硅层（20; 122）可以以相对于彼此的任何顺序沉积。碳化硅层（18; 124）在蚀刻通过绝缘层（16; 116,120）时保持通孔或沟槽的临界尺寸，而氮化硅层（20; 122）抑制抗蚀剂的失效机理中毒该方法适用于单镶嵌工艺，但也可用于双镶嵌铜工艺。

3. 发明申请

US20050255687A1 Plasma treatment for silicon-based dielectrics 有权
标题翻译：硅基电介质的等离子体处理
公开(公告)号：US20050255687A1
公开(公告)日：2005-11-17
申请号：US10843957
申请日：2004-05-11
申请人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
发明人： Ping Jiang , Hyesook Hong , Ting Tsui , Robert Kraft
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/02123 , H01L21/0234 , H01L21/3105 , H01L21/316 , H01L21/76807 , H01L21/76808
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).
摘要翻译：本发明的一个实施例是制造半导体晶片的方法。该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤（步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

4. 发明授权

US07282436B2 Plasma treatment for silicon-based dielectrics 有权
标题翻译：硅基电介质的等离子体处理
公开(公告)号：US07282436B2
公开(公告)日：2007-10-16
申请号：US10843957
申请日：2004-05-11
申请人： Ping Jiang , Hyesook Hong , Ting Yiu Tsui , Robert Kraft
发明人： Ping Jiang , Hyesook Hong , Ting Yiu Tsui , Robert Kraft
IPC分类号： H01L21/4763
CPC分类号： H01L21/02123 , H01L21/0234 , H01L21/3105 , H01L21/316 , H01L21/76807 , H01L21/76808
摘要： An embodiment of the invention is a method of manufacturing a semiconductor wafer. The method includes depositing spin-on-glass material over the semiconductor wafer (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over the spin-on-glass material (step 214), patterning the photoresist layer (step 214), and then etching the semiconductor wafer (step 216). Another embodiment of the invention is a method of manufacturing a dual damascene back-end layer on a semiconductor wafer. The method includes depositing spin-on-glass material over the dielectric layer and within the via holes (step 208), modifying a top surface of the spin-on glass material to form a SiO2 layer (step 210), applying a vapor prime (step 212), forming a photoresist layer over said spin-on-glass material (step 214), patterning the photoresist layer (step 214), and etching trench spaces (step 216).
摘要翻译：本发明的一个实施例是制造半导体晶片的方法。该方法包括在半导体晶片上沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤210），施加蒸发（步骤212），在旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214），然后蚀刻半导体晶片（步骤216）。本发明的另一实施例是在半导体晶片上制造双镶嵌后端层的方法。该方法包括在电介质层上和通孔内沉积旋涂玻璃材料（步骤208），修饰旋涂玻璃材料的顶表面以形成SiO 2层（步骤（步骤212），在所述旋涂玻璃材料上形成光致抗蚀剂层（步骤214），图案化光致抗蚀剂层（步骤214）和蚀刻沟槽空间（步骤216）。

5. 发明授权

US07214609B2 Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities 有权
标题翻译：用于形成单镶嵌通孔或沟槽的方法以及通过空腔形成双镶嵌
公开(公告)号：US07214609B2
公开(公告)日：2007-05-08
申请号：US10313491
申请日：2002-12-05
申请人： Ping Jiang , Rob Kraft , Guoqiang Xing , Karen H. R. Kirmse , Eden Zielinski
发明人： Ping Jiang , Rob Kraft , Guoqiang Xing , Karen H. R. Kirmse , Eden Zielinski
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76802
摘要： Methods are disclosed for forming trench or via cavities in a single damascene interconnect structure, comprising etching a dielectric layer to form a cavity there and to expose an underlying etch-stop layer, and etching the exposed etch-stop layer to extend the cavity and to expose a conductive feature in an existing interconnect structure, wherein etching the portion of the dielectric layer and etching the exposed portion of the etch-stop layer are performed concurrently with substantially no intervening processing steps therebetween. Also disclosed are methods of forming a via cavity in a dual damascene interconnect structure, comprising forming an etch-stop layer over an existing interconnect structure, forming a dielectric layer over the etch-stop layer, etching a portion of the dielectric layer to form a via cavity in the dielectric layer and to expose a portion of the etch-stop layer, and etching the etch-stop layer to extend the via cavity, where the dielectric layer is covered during etching of the etch-stop layer.
摘要翻译：公开了用于在单个镶嵌互连结构中形成沟槽或通孔腔的方法，包括蚀刻介电层以在其中形成空腔并暴露下面的蚀刻停止层，以及蚀刻暴露的蚀刻停止层以延伸空腔，并且暴露现有互连结构中的导电特征，其中蚀刻介电层的一部分并蚀刻蚀刻停止层的暴露部分同时进行，其间基本上没有中间处理步骤。还公开了在双镶嵌互连结构中形成通孔腔的方法，包括在现有互连结构上形成蚀刻停止层，在蚀刻停止层上形成电介质层，蚀刻介电层的一部分以形成并且暴露蚀刻停止层的一部分，以及蚀刻蚀刻停止层以延伸通孔腔，其中介电层在蚀刻停止层的蚀刻期间被覆盖。

6. 发明授权

US06410426B1 Damascene cap layer process for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的镶嵌帽层工艺
公开(公告)号：US06410426B1
公开(公告)日：2002-06-25
申请号：US09901392
申请日：2001-07-09
申请人： Guoqiang Xing , Ping Jiang
发明人： Guoqiang Xing , Ping Jiang
IPC分类号： H01L214763
CPC分类号： H01L21/76808 , H01L21/76802 , Y10S438/97
摘要： The invention describes a method for forming integrated circuit interconnects. A capping layer (50) is formed on a low k dielectric layer (40). The capping layer (50) and the low k dielectric layer (40) are etched to form a via and/or trench in the low k dielectric (4) which is filled with a conducting material (90) (95).
摘要翻译：本发明描述了一种用于形成集成电路互连的方法。在低k电介质层（40）上形成覆盖层（50）。蚀刻覆盖层（50）和低k电介质层（40）以在填充有导电材料（90）（95）的低k电介质（4）中形成通孔和/或沟槽。

7. 发明申请

US20070042599A1 Methods to facilitate etch uniformity and selectivity 有权
标题翻译：促进蚀刻均匀性和选择性的方法
公开(公告)号：US20070042599A1
公开(公告)日：2007-02-22
申请号：US11207493
申请日：2005-08-19
申请人： Ting Tsui , Jeannette Jacques , Robert Kraft , Ping Jiang
发明人： Ting Tsui , Jeannette Jacques , Robert Kraft , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76807
摘要： A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
摘要翻译：用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。第一互连层形成在半导体本体上。第一介电层形成在第一互连层上。改变第一介电层的蚀刻速率。在第一电介质层上形成第二电介质层。然后改变第二电介质层的蚀刻速率。执行沟槽蚀刻以在第二介电层内形成沟槽。执行通孔蚀刻以在第一介电层内形成通孔腔。空腔填充有导电材料，然后平坦化以除去多余的填充材料。

8. 发明申请

US20050245074A1 In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures 审中-公开
标题翻译：在形成半导体互连结构中与镶嵌加工相关联的原位蚀刻停止蚀刻和灰化
公开(公告)号：US20050245074A1
公开(公告)日：2005-11-03
申请号：US10834436
申请日：2004-04-29
申请人： Ping Jiang , Robert Kraft
发明人： Ping Jiang , Robert Kraft
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/76807
摘要： One or more aspects of the subject disclosure pertain to forming single or dual damascene interconnect structures in the fabrication of semiconductor devices. The interconnect structures are formed in manners that mitigate one or more adverse effects associated with conventional techniques. One or more aspects of the invention may be employed, for example, to facilitate better via critical dimension (CD) control, improve selectivity of etch-stop layer to inter layer dielectric (ILD) and/or intra-metal dielectric (IMD) material, and/or to simplify and make the fabrication process more efficient and/or cost effective.
摘要翻译：本公开内容的一个或多个方面涉及在半导体器件的制造中形成单镶嵌或双镶嵌互连结构。互连结构以减轻与常规技术相关的一个或多个不利影响的方式形成。本发明的一个或多个方面可用于例如促进更好的通过临界尺寸（CD）控制，提高蚀刻停止层对层间电介质（ILD）和/或金属间电介质（IMD）材料的选择性，和/或简化并使制造过程更有效和/或成本有效。

9. 发明授权

US06797633B2 In-situ plasma ash/treatment after via etch of low-k films for poison-free dual damascene trench patterning 有权
标题翻译：原位等离子体灰/通过蚀刻低k膜后的无毒双镶嵌沟槽图案处理
公开(公告)号：US06797633B2
公开(公告)日：2004-09-28
申请号：US09966605
申请日：2001-09-28
申请人： Ping Jiang , Robert Kraft , Kenneth J. Newton , Daty M. Rogers
发明人： Ping Jiang , Robert Kraft , Kenneth J. Newton , Daty M. Rogers
IPC分类号： H01L21302
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76808 , H01L21/76826
摘要： After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.
摘要翻译：在经过蚀刻之后，用原位O 2等离子体处理低k电介质层（104）。抵抗中毒是由导致低k膜（104）如OSG和DUV抗蚀剂（130,132）之间的相互作用的N源引起的。原位等离子体处理立即消除中毒源，以减少或消除沟槽图案化的中毒。

10. 发明授权

US07341941B2 Methods to facilitate etch uniformity and selectivity 有权
标题翻译：促进蚀刻均匀性和选择性的方法
公开(公告)号：US07341941B2
公开(公告)日：2008-03-11
申请号：US11207493
申请日：2005-08-19
申请人： Ting Y. Tsui , Jeannette M. Jacques , Robert Kraft , Ping Jiang
发明人： Ting Y. Tsui , Jeannette M. Jacques , Robert Kraft , Ping Jiang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76825 , H01L21/76807
摘要： A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
摘要翻译：用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。第一互连层形成在半导体本体上。第一介电层形成在第一互连层上。改变第一介电层的蚀刻速率。在第一电介质层上形成第二电介质层。然后改变第二电介质层的蚀刻速率。执行沟槽蚀刻以在第二介电层内形成沟槽。执行通孔蚀刻以在第一介电层内形成通孔腔。空腔填充有导电材料，然后平坦化以除去多余的填充材料。

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