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1. 发明申请

US20120199896A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE FOR SUPPRESSING DETERIORATION IN JUNCTION BREAKDOWN VOLTAGE AND SURFACE BREAKDOWN VOLTAGE OF TRANSISTOR 失效
标题翻译：非易失性半导体存储器件，用于抑制断路电压和晶体管表面断开电压的检测
公开(公告)号：US20120199896A1
公开(公告)日：2012-08-09
申请号：US13234613
申请日：2011-09-16
申请人： Mitsuhiro NOGUCHI , Hiroyuki Kutsukake , Masato Endo
发明人： Mitsuhiro NOGUCHI , Hiroyuki Kutsukake , Masato Endo
IPC分类号： H01L27/088 , H01L27/06 , H01L29/78
CPC分类号： H01L27/11524 , H01L27/11519
摘要： According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on the gate insulating film, a sidewall insulating film on both side surfaces of the gate electrode, a source diffusion layer corresponding to the sidewall insulating film, a first hollow formed in a position at a height less than a bottom surface of the gate insulating film directly below an outer side surface of the sidewall insulating film of another side of the gate electrode, a second hollow formed in the first hollow at a position at a height less than the first hollow, and a drain diffusion layer corresponding to another side of the gate electrode and including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括多个存储单元和晶体管。晶体管包括栅极绝缘膜，栅极绝缘膜上的栅电极，栅电极的两个侧表面上的侧壁绝缘膜，对应于侧壁绝缘膜的源极扩散层，形成在位于高度小于栅电极另一侧的侧壁绝缘膜的外侧表面正下方的栅极绝缘膜的底表面，在第一中空部分中形成的第二中空在比第一中空部的高度低的位置处，以及与栅电极的另一侧对应的漏极扩散层，并且包括形成在第二中空部的底面上的低浓度漏极区域和高浓度漏极区域。

2. 发明授权

US08319316B2 Depletion MOS transistor and enhancement MOS transistor 有权
标题翻译：消耗MOS晶体管和增强型MOS晶体管
公开(公告)号：US08319316B2
公开(公告)日：2012-11-27
申请号：US12788784
申请日：2010-05-27
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Yoshiko Kato , Mitsuhiro Noguchi , Masato Endo
IPC分类号： H01L21/02
CPC分类号： H01L29/0847 , H01L21/823418 , H01L27/088 , H01L27/11526 , H01L27/11529 , H01L29/41775 , H01L29/7838
摘要： A semiconductor memory device includes a first transistor. The first transistor includes a gate electrode, a channel region, a source region, a source region, an overlapping region, a contact region, and an impurity diffusion region. The channel region has a first impurity concentration. The source and drain regions have a second impurity concentration. The overlapping region is formed in the semiconductor layer where the channel region overlaps the source region and the drain region, and has a third impurity concentration. The contact region has a fourth impurity concentration. The impurity diffusion region has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region is in contact with the contact region and away from the overlapping region and positioned at least in a region between the contact region and the overlapping region.
摘要翻译：半导体存储器件包括第一晶体管。第一晶体管包括栅电极，沟道区，源极区，源极区，重叠区，接触区和杂质扩散区。沟道区具有第一杂质浓度。源区和漏区具有第二杂质浓度。重叠区域形成在沟道区域与源极区域和漏极区域重叠的半导体层中，并且具有第三杂质浓度。接触区域具有第四杂质浓度。杂质扩散区具有比第二杂质浓度高的第五杂质浓度并低于第四杂质浓度。杂质扩散区域与接触区域接触并且远离重叠区域并且至少位于接触区域和重叠区域之间的区域中。

3. 发明申请

US20100124117A1 NONVOLATILE SEMICONDUCTOR MEMORY 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20100124117A1
公开(公告)日：2010-05-20
申请号：US12618200
申请日：2009-11-13
申请人： Hiroyuki KUTSUKAKE , Kenji GOMIKAWA , Mitsuhiro NOGUCHI , Kikuko SUGIMAE , Masato Endo , Takuya FUTATSUYAMA , Koji KATO , Kanae UCHIDA
发明人： Hiroyuki KUTSUKAKE , Kenji GOMIKAWA , Mitsuhiro NOGUCHI , Kikuko SUGIMAE , Masato Endo , Takuya FUTATSUYAMA , Koji KATO , Kanae UCHIDA
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
摘要翻译：存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

4. 发明授权

US08625349B2 Potential relationship in an erasing operation of a nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器的擦除操作中的潜在关系
公开(公告)号：US08625349B2
公开(公告)日：2014-01-07
申请号：US12618200
申请日：2009-11-13
申请人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
发明人： Hiroyuki Kutsukake , Kenji Gomikawa , Mitsuhiro Noguchi , Kikuko Sugimae , Masato Endo , Takuya Futatsuyama , Koji Kato , Kanae Uchida
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/16 , H01L27/11521 , H01L27/11526
摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.
摘要翻译：存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。

5. 发明授权

US08604517B2 Non-volatile semiconductor memory device for suppressing deterioration in junction breakdown voltage and surface breakdown voltage of transistor 失效
标题翻译：用于抑制晶体管的结击穿电压和表面击穿电压的劣化的非易失性半导体存储器件
公开(公告)号：US08604517B2
公开(公告)日：2013-12-10
申请号：US13234613
申请日：2011-09-16
申请人： Mitsuhiro Noguchi , Hiroyuki Kutsukake , Masato Endo
发明人： Mitsuhiro Noguchi , Hiroyuki Kutsukake , Masato Endo
IPC分类号： H01L29/66
CPC分类号： H01L27/11524 , H01L27/11519
摘要： According to one embodiment, a non-volatile semiconductor memory device includes a plurality of memory cells and a transistor. The transistor includes a gate insulating film, a gate electrode on the gate insulating film, a sidewall insulating film on both side surfaces of the gate electrode, a source diffusion layer corresponding to the sidewall insulating film, a first hollow formed in a position at a height less than a bottom surface of the gate insulating film directly below an outer side surface of the sidewall insulating film of another side of the gate electrode, a second hollow formed in the first hollow at a position at a height less than the first hollow, and a drain diffusion layer corresponding to another side of the gate electrode and including a low-concentration drain region formed on a bottom surface of the second hollow and a high-concentration drain region.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括多个存储单元和晶体管。晶体管包括栅极绝缘膜，栅极绝缘膜上的栅电极，栅电极的两个侧表面上的侧壁绝缘膜，对应于侧壁绝缘膜的源极扩散层，形成在位于高度小于栅电极另一侧的侧壁绝缘膜的外侧表面正下方的栅极绝缘膜的底表面，在第一中空部分中形成的第二中空在比第一中空部的高度低的位置处，以及与栅电极的另一侧对应的漏极扩散层，并且包括形成在第二中空部的底面上的低浓度漏极区域和高浓度漏极区域。

6. 发明授权

US08519467B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08519467B2
公开(公告)日：2013-08-27
申请号：US13051516
申请日：2011-03-18
申请人： Masato Endo , Mitsuhiro Noguchi
发明人： Masato Endo , Mitsuhiro Noguchi
IPC分类号： H01L27/06
CPC分类号： H01L27/105 , H01L27/0629 , H01L27/11531 , H01L28/20
摘要： According to one embodiment, a semiconductor device includes a first resistance element including a first conductive material, an inter-gate insulation film formed on both ends of the first conductive material in a first direction, and a second conductive material formed above the first conductive material and configured to connect with the first conductive material via a first connection region from which the inter-gate insulation film is removed, and a second resistance element including a third conductive material, the inter-gate insulation film formed on both ends of the third conductive material in the first direction, and a fourth conductive material formed above the third conductive material and configured to connect with the third conductive material via a second connection region from which the inter-gate insulation film is removed, wherein a length of the second connection region is greater than a length of the first connection region in the first direction.
摘要翻译：根据一个实施例，半导体器件包括第一电阻元件，第一电阻元件包括第一导电材料，在第一方向上形成在第一导电材料的两端上的栅极间绝缘膜和形成在第一导电材料上方的第二导电材料并且被配置为经由去除所述栅极间绝缘膜的第一连接区域与所述第一导电材料连接，以及包括第三导电材料的第二电阻元件，所述栅极间绝缘膜形成在所述第三导电材料在第一方向上形成，第四导电材料形成在第三导电材料之上，并被配置为经由去除栅间绝缘膜的第二连接区域与第三导电材料连接，其中第二连接区域大于第一方向上的第一连接区域的长度。

7. 发明授权

US08288751B2 Semiconductor memory device and manufacturing method of the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US08288751B2
公开(公告)日：2012-10-16
申请号：US12759107
申请日：2010-04-13
申请人： Mitsuhiko Noda , Mitsuhiro Noguchi , Hiroomi Nakajima , Masato Endo
发明人： Mitsuhiko Noda , Mitsuhiro Noguchi , Hiroomi Nakajima , Masato Endo
IPC分类号： H01L27/11
CPC分类号： H01L27/105 , H01L27/1021 , H01L27/1052 , H01L27/24
摘要： A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.
摘要翻译：半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储器单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，第一阱形成在半导体衬底中并具有第一导电类型，元件隔离绝缘膜，其包括比第一阱中的第一阱的底表面浅的底表面，并且埋在半导体衬底中，第二阱包括比第一阱的底表面浅的底表面在第一阱中沿着元件隔离绝缘膜的至少一部分的底表面形成并由具有第二导电类型的杂质和与第一阱电连接的接触线形成。

8. 发明申请

US20100258783A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100258783A1
公开(公告)日：2010-10-14
申请号：US12759107
申请日：2010-04-13
申请人： Mitsuhiko NODA , Mitsuhiro Noguchi , Hiroomi Nakajima , Masato Endo
发明人： Mitsuhiko NODA , Mitsuhiro Noguchi , Hiroomi Nakajima , Masato Endo
IPC分类号： H01L27/11 , H01L21/8239 , H01L45/00
CPC分类号： H01L27/105 , H01L27/1021 , H01L27/1052 , H01L27/24
摘要： A semiconductor memory device includes a plurality of memory cell arrays each includes a plurality of memory cells, the plurality of memory cell arrays being stacked on a semiconductor substrate to form a three-dimensional structure, a first well formed in the semiconductor substrate and having a first conductivity type, an element isolation insulating film including a bottom surface shallower than a bottom surface of the first well in the first well, and buried in the semiconductor substrate, a second well including a bottom surface shallower than the bottom surface of the first well in the first well, formed along a bottom surface of at least a portion of the element isolation insulating film, and made of an impurity having a second conductivity type, and a contact line electrically connected to the first well.
摘要翻译：半导体存储器件包括多个存储单元阵列，每个存储单元阵列包括多个存储器单元，多个存储单元阵列堆叠在半导体衬底上以形成三维结构，第一阱形成在半导体衬底中并具有第一导电类型，元件隔离绝缘膜，其包括比第一阱中的第一阱的底表面浅的底表面，并且埋在半导体衬底中，第二阱包括比第一阱的底表面浅的底表面在第一阱中沿着元件隔离绝缘膜的至少一部分的底表面形成并由具有第二导电类型的杂质和与第一阱电连接的接触线形成。

9. 发明授权

US09070743B2 Semiconductor memory and manufacturing method of the same 有权
标题翻译：半导体存储器及其制造方法相同
公开(公告)号：US09070743B2
公开(公告)日：2015-06-30
申请号：US13413952
申请日：2012-03-07
申请人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
发明人： Yoshiko Kato , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
IPC分类号： H01L29/788 , H01L21/762 , H01L29/66 , H01L29/792 , H01L27/115
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.
摘要翻译：根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管并且其包括由第二隔离绝缘体围绕的第二有源区。第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

10. 发明申请

US20130062680A1 SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：半导体存储器及其制造方法
公开(公告)号：US20130062680A1
公开(公告)日：2013-03-14
申请号：US13413952
申请日：2012-03-07
申请人： Yoshiko KATO , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
发明人： Yoshiko KATO , Masato Endo , Mitsuhiko Noda , Mitsuhiro Noguchi
IPC分类号： H01L27/105 , H01L21/8239
CPC分类号： H01L21/76229 , H01L27/11519 , H01L27/11529 , H01L27/11546 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： According to one embodiment, a semiconductor memory includes a memory cell in a memory cell array which is provided in a semiconductor substrate and which includes a first active region surrounded by a first isolation insulator, a transistor in a transistor region which is provided in the semiconductor substrate and which includes second active regions surrounded by a second isolation insulator. The second isolation insulator includes a first film, and a second film between the first film and the second active region, and the upper surface of the first film is located closer to the bottom of the semiconductor substrate than the upper surface of the second film.
摘要翻译：根据一个实施例，半导体存储器包括设置在半导体衬底中的存储单元阵列中的存储单元，其包括由第一隔离绝缘体围绕的第一有源区，设置在半导体中的晶体管区中的晶体管并且其包括由第二隔离绝缘体围绕的第二有源区。第二隔离绝缘体包括第一膜和在第一膜和第二有源区之间的第二膜，并且第一膜的上表面比第二膜的上表面更靠近半导体衬底的底部。

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