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1. 发明专利

JP2012066286A Soldering device 有权
标题翻译：焊接设备
公开(公告)号：JP2012066286A
公开(公告)日：2012-04-05
申请号：JP2010213779
申请日：2010-09-24
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KAWABATA RYOHEI , IDETA GORO
IPC分类号： B23K1/08 , B23K101/42 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To obtain a jetting nozzle with which the stable solder jet is supplied and defective soldering is reduced without generating the withering of a flux about the jetting nozzle of a soldering device.SOLUTION: The soldering device includes: a solder tank for storing a molten solder; a jetting nozzle which is arranged on the solder tank and the upper part of which is opened; and a circulating mechanism for supplying the molten solder stored in the solder tank to the jetting nozzle. The jetting nozzle has an outer wall with which the circumference is surrounded and a partition which is lower than the outer wall in the height and the upper end of the inside of the outer wall is covered with a belt-like member which is excellent in the wettability to the molten solder.
摘要翻译：要解决的问题：为了获得供应稳定的焊料射流的喷射喷嘴，并且不会在焊接装置的喷射喷嘴周围产生焊剂的枯萎而减少焊接不良。焊接装置包括：用于储存熔融焊料的焊料槽; 喷射喷嘴，其布置在所述焊料槽上并且其上部被打开; 以及用于将存储在焊料槽中的熔融焊料供给到喷嘴的循环机构。喷射喷嘴具有围绕圆周的外壁，并且在外壁的内部的高度和外壁的低于外壁的隔壁上覆盖有一个带状部件，该带状部件在对熔融焊料的润湿性。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2011189395A Jig for measuring height of molten solder jet 审中-公开
标题翻译：用于测量熔体喷枪的高度
公开(公告)号：JP2011189395A
公开(公告)日：2011-09-29
申请号：JP2010059347
申请日：2010-03-16
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SATO KOHEI , IDETA GORO , YANAGIMOTO TATSUNORI
IPC分类号： B23K1/08 , B23K1/00 , B23K101/42 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To easily and quantitatively measure the height of molten solder ejected from a jet nozzle in a method of soldering in which the molten solder is jetted and applied to a print wiring board.
SOLUTION: The invented jig comprises a hollow box-shaped housing having an open bottom and a plurality of members placed above the top side of the jet nozzle. The plurality of the members are respectively arranged parallel to the top side of the jet nozzle at given different distances from the top side of the jet nozzle so that the members are set like a staircase in the box-shaped housing.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了容易且定量地测量从熔喷焊料喷射并施加到印刷线路板上的焊接方法中从喷嘴喷射的熔融焊料的高度。解决方案：本发明的夹具包括具有开口底部的空心箱形壳体和放置在喷嘴顶部上方的多个构件。多个构件分别平行于喷嘴的顶侧布置，距离喷嘴的顶侧给定的不同距离，使得构件在箱形壳体中被设置为阶梯状。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2011171491A Electronic circuit board and method of manufacturing the same 有权
标题翻译：电子电路板及其制造方法
公开(公告)号：JP2011171491A
公开(公告)日：2011-09-01
申请号：JP2010033533
申请日：2010-02-18
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： ABE HAJIME , IDETA GORO , SATO KOHEI , TANABE TAKESHI , UCHIDA SACHIHISA
IPC分类号： H05K1/02 , H05K1/18
摘要： PROBLEM TO BE SOLVED: To provide an electronic circuit board which can more easily be designed by suppressing the thermal expansion of a board, and to provide a manufacturing method of the same.
SOLUTION: The electronic circuit board 1 comprises the substrate 2 having recesses 4 on surfaces thereof and composed of a material containing a resin, electrode pads 5 formed on the side walls 4a of the recesses 4 and the surfaces of the substrate 2 and composed of a material containing a metal, and an external terminal 3 having conductivity and soldered to the electrode pads 5 in such a manner that the external terminal sandwiches the substrate 2 from the front surface side and the opposing rear surface side of the substrate 2.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过抑制板的热膨胀更容易设计的电子电路板，并提供其制造方法。解决方案：电子电路板1包括在其表面上具有凹部4并由包含树脂的材料构成的基板2，形成在凹部4的侧壁4a上的电极焊盘5和基板2的表面以及由含有金属的材料构成，外部端子3具有导电性，并以这样的方式焊接到电极焊盘5，使得外部端子从基板2的表面侧和相对的后表面侧夹持基板2。版权所有（C）2011，JPO＆INPIT

4. 发明专利

JP2010283122A Solder bonding device, solder bonding part, solder bonding method, and method of manufacturing printed wiring board 有权
标题翻译：焊接接合装置，焊接接合部件，焊接接合方法和制造印刷电路板的方法
公开(公告)号：JP2010283122A
公开(公告)日：2010-12-16
申请号：JP2009134979
申请日：2009-06-04
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： IDETA GORO , MURAI JUNICHI , YAMASHITA HIROYOSHI , SASAKI SHUNSUKE
IPC分类号： H05K3/34 , B23K1/00 , B23K1/005 , B23K1/08 , B23K3/04
摘要： PROBLEM TO BE SOLVED: To provide a solder bonding device, a solder bonding part and a solder bonding method that suppress occurrence of a bridge defect or icicle defect between adjacent electrodes when an electronic component having an electrode lead is mounted on a printed wiring board by soldering the electronic component to a through hole electrode of the printed wiring board, and to provide a method of manufacturing printed wiring board.
SOLUTION: A heating device 11 selectively heats solder 1 supplied to the through hole electrode 7 to delay solidification of the supplied solder 1. Consequently, occurrence of a bridge defect or icicle defect between adjacent electrode leads 6 can be suppressed.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种当具有电极引线的电子部件安装在印刷电路板上时，能够抑制相邻电极之间的桥接缺陷或冰柱缺陷的发生的焊接接合装置，焊接接合部和焊接接合方法通过将电子部件焊接到印刷电路板的通孔电极上的布线板，并提供制造印刷线路板的方法。解决方案：加热装置11选择性地加热提供给通孔电极7的焊料1，以延迟提供的焊料1的固化。因此，可以抑制相邻电极引线6之间的桥缺陷或冰柱缺陷的发生。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JP2009076727A Printed wiring board, electronic equipment using the same, and manufacturing method thereof 审中-公开
标题翻译：印刷电路板，使用该印刷电路板的电子设备及其制造方法
公开(公告)号：JP2009076727A
公开(公告)日：2009-04-09
申请号：JP2007244937
申请日：2007-09-21
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TANABE TAKESHI , MURAI JUNICHI , IDETA GORO
IPC分类号： H05K3/34 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board which can prevent disconnection of a wiring pattern even when lead-free solder is used and is reliable, electronic equipment using the same, and a manufacturing method thereof.
SOLUTION: Disclosed is the printed wiring board 1 characterized in that a land 3 provided to a through hole 2 comprises a plurality of conductive layers. As a concrete example, the plurality of conductive layers comprise a first conductive layer 31 formed at an extension portion of the wiring pattern 5 and connected to the wiring pattern 5, and a second conductive layer 32 formed on a top surface side of the first conductive layer 31 and electrically and physically connected to the first conductive layer 31 at an end on the side of the through hole 2.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供即使在使用无铅焊料时也能够防止布线图案断开且可靠的印刷布线板，使用该布线板的电子设备及其制造方法。解决方案：公开了印刷电路板1，其特征在于，设置在通孔2上的焊盘3包括多个导电层。作为具体实例，多个导电层包括形成在布线图案5的延伸部分并连接到布线图案5的第一导电层31和形成在第一导电层的顶表面侧上的第二导电层32 层31，并且在通孔2的一侧的端部与第一导电层31电连接并物理连接。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2006245620A Method for manufacturing insertion-mounting type semiconductor device 有权
标题翻译：制造插入式半导体器件的方法
公开(公告)号：JP2006245620A
公开(公告)日：2006-09-14
申请号：JP2006167727
申请日：2006-06-16
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： HAYASHI KENICHI , KAWATO HISASHI , MURAI JUNICHI , IDETA GORO
IPC分类号： H01L23/50
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device capable of being mounted easily and surely on an external substrate and the like through soldering. SOLUTION: A semiconductor device is provided with a first lead portion 21 with a large width, second lead portion 22 with narrow width, third lead portion 23, which is inserted into an external substrate, and gap control portion 9, which keeps a gap constant between the semiconductor device and the external substrate. The method for manufacturing the semiconductor device is configured, in such a way that the lead is formed by linearly cutting a lead frame having a broad portion corresponding to the first lead portion 21, narrow portion corresponding to the third lead portion 23, and tie bar portion 11, which couples the broad portion and narrow portion, and in which two notch portions 31 are formed in the region on the side of the narrow portion. Furthermore, both notch portions 31 are made to be located on both sides of the range of the narrow portion in terms of the lead width direction, located on the extension of both sides of the broad portion and is provided with the gap control means 9, in advance. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种能够通过焊接容易且可靠地安装在外部基板等上的半导体器件的制造方法。解决方案：半导体器件设置有具有宽度的第一引线部分21和窄的第二引线部分22，被插入到外部基板中的第三引线部分23和保持在外部基板中的间隙控制部分9 半导体器件和外部衬底之间的间隙常数。半导体器件的制造方法被构造成使引线通过直线切割具有与第一引线部分21相对应的宽部分的引线框架，对应于第三引线部分23的窄部分和连接杆部分11，其连接宽部分和窄部分，并且其中在狭窄部分侧面上的区域中形成有两个切口部分31。此外，两个切口部31被制成位于宽度方向上的狭窄部分的范围的两侧，位于宽部的两侧的延伸部上，并且设置有间隙控制装置9，提前。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2004066305A Solder 审中-公开
公开(公告)号：JP2004066305A
公开(公告)日：2004-03-04
申请号：JP2002230149
申请日：2002-08-07
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MURAI JUNICHI , IDETA GORO , MURAKAMI KOHEI
IPC分类号： B23K35/26 , C22C13/00 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide lead-free solder in which the amount of dross to be formed is suppressed, and which has excellent mechanical properties or the like.
SOLUTION: The solder comprises Sn, Ag, and Cu, and P with a concentration in which crystallization does not occur after soldering is incorporated therein. Particularly, the content of Ag is controlled, by weight, to about 3.0%, Cu to about 0.5%, and P to about 0.002 to 0.008%. Further, as the one for correcting the P concentration in the solder, P having a concentration with which it perfectly dissolves in Sn at about 250°C is comprised. Particularly, Sn, Ag, Cu, and about ≤0.065% P are incorporated therein.
COPYRIGHT: (C)2004,JPO

8. 发明专利

JP2002331386A SOLDER AND SOLDERED WIRING SUBSTRATE USING THE SAME 失效
公开(公告)号：JP2002331386A
公开(公告)日：2002-11-19
申请号：JP2001137360
申请日：2001-05-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： IDETA GORO , MURAI JUNICHI , SAKAGAMI YUKINOBU , MURAKAMI KOHEI
IPC分类号： B23K35/26 , B23K1/00 , C22C13/00 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide solder containing only an extremely little Pb, low in a melting point, excellent in wettability, and excellent in mechanical properties, and provide a soldered wiring substrate using the soldering not exerting a bad influence on the environment, and excellent in reliability for long term connection. SOLUTION: The solder contains Sn as a main component, besides Ag and Cu, and contain an extremely little amount of Pb, in particular, 1-3 wt.% Ag, 0.3-1 wt.% Cu and 0.3-2.0 wt.% Pb.

9. 发明专利

JPH11265976A POWER-SEMICONDUCTOR MODULE AND ITS MANUFACTURE 失效
公开(公告)号：JPH11265976A
公开(公告)日：1999-09-28
申请号：JP6851098
申请日：1998-03-18
申请人： MITSUBISHI ELECTRIC CORP
发明人： KAMIGAI YASUMI , IDETA GORO , MATSUMOTO HIDEO
IPC分类号： H01L25/07 , H01L25/18 , H05K1/02 , H05K3/00 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To prevent the occurrence of cracks in the bonding material, which connects an insulating member and a base plate by absorbing the mutual thermal deformation differences caused by the difference in thermal expansion coefficients of the insulating member and the base plate without increasing thermal resistance. SOLUTION: At the junction part of a base plate to an insulating member 2, a protruding step difference part 5 having the area smaller than the junction area is provided. At the side-surface part of this protruding step difference part, a thick bonding material part 10 having the height of a filler surface 11 in correspondence with the step difference is formed. The above described protruding step difference part is formed by bonding the plate material having the specified shape to the flat base plate. Furthermore, the above described step difference part has at least three projections not on the same straight line at the junction surface with the insulating member. Furthermore, the process, which applies solder resist around the bonding-material arranged part around the protruding step difference part of the base plate, is provided.

10. 发明专利

JPH09115955A SEMICONDUCTOR DEVICE PACKING SUBSTRATE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH09115955A
公开(公告)日：1997-05-02
申请号：JP26701995
申请日：1995-10-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： ADACHI TERU , IDETA GORO , FUJINO JUNJI , HIROTA MIHO
IPC分类号： H01L21/60 , H01L21/321
摘要： PROBLEM TO BE SOLVED: To prevent disconnection due to thermal stress caused by the difference in thermal expansion of coefficient between a semiconductor device and a circuit board and to easy recover when the connection failure occurs in a method for packaging the semiconductor device on the circuit board. SOLUTION: A protruding electrode 9 is formed on an electrode pad 2 of a semiconductor device 1 and an adhesive sheet 15 is supplied to a circuit board 14. The circuit board 14 is heated and the adhesive sheet 15 is softened, the conductor pattern of the semiconductor device is aligned to that of the circuit board and the semiconductor device 1 and the circuit board 14 are thermocompression bonded at a temperature where the semiconductor device 1 and the circuit board 14 can be disconnected by re-heating. After the thermocompression bonding, the conduction test between the semiconductor device and the circuit board is made and the semiconductor device and the circuit board are sealed due to thermocompression bonding when they conduct. They are heated again in case of conduction failure, thus releasing the semiconductor device from the circuit board.

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