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1. 发明申请

US20050245075A1 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US20050245075A1
公开(公告)日：2005-11-03
申请号：US11174595
申请日：2005-07-06
申请人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
发明人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
IPC分类号： G03F7/40 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L27/15
CPC分类号： H01L21/76811 , H01L21/76808 , H01L21/76813
摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.

2. 发明授权

US06927495B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06927495B2
公开(公告)日：2005-08-09
申请号：US10642279
申请日：2003-08-18
申请人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
发明人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
IPC分类号： G03F7/40 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L27/15 , H10L23/48 , H10L23/52 , H10L29/40
CPC分类号： H01L21/76811 , H01L21/76808 , H01L21/76813
摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.
摘要翻译：公开了具有精密加工的双镶嵌结构的半导体器件。半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有沟槽图案。至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。

3. 发明授权

US07341937B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07341937B2
公开(公告)日：2008-03-11
申请号：US11174595
申请日：2005-07-06
申请人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
发明人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
IPC分类号： H01L21/4763
CPC分类号： H01L21/76811 , H01L21/76808 , H01L21/76813
摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.
摘要翻译：公开了具有精密加工的双镶嵌结构的半导体器件。半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有沟槽图案。至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。

4. 发明申请

US20070117405A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070117405A1
公开(公告)日：2007-05-24
申请号：US11655261
申请日：2007-01-19
申请人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
发明人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
IPC分类号： H01L21/31
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76832
摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
摘要翻译：半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210， SUB>膜212和形成在其上的SiCN膜214。第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。第二SiOC膜210的碳含量被调整为大于第一SiOC膜204的碳含量。这使得可以在保持绝缘中间层的低介电常数的同时提高绝缘中间层与其它绝缘层的粘附性。

5. 发明申请

US20050170633A1 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050170633A1
公开(公告)日：2005-08-04
申请号：US11048929
申请日：2005-02-03
申请人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
发明人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
IPC分类号： H01L23/522 , H01L21/316 , H01L21/4763 , H01L21/768
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76832
摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
摘要翻译：半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210， SUB>膜212和形成在其上的SiCN膜214。第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。第二SiOC膜210的碳含量被调节为大于第一SiOC膜204的碳含量。这使得可以在保持绝缘中间层的低介电常数的同时，改善绝缘中间层与其它绝缘层的粘附性。

6. 发明授权

US5810932A Plasma generating apparatus used for fabrication of semiconductor device 失效
标题翻译：用于制造半导体器件的等离子体发生装置
公开(公告)号：US5810932A
公开(公告)日：1998-09-22
申请号：US692283
申请日：1996-08-05
申请人： Yasuhiko Ueda , Hideaki Kawamoto , Hidenobu Miyamoto
发明人： Yasuhiko Ueda , Hideaki Kawamoto , Hidenobu Miyamoto
IPC分类号： H01J37/32 , H05H1/46 , H05H1/00 , C23F1/02
CPC分类号： H01J37/32082 , H01J37/3266 , H05H1/46
摘要： An apparatus for generating plasma, includes a cylindrical vacuum chamber made of dielectric substance, the chamber being open only at a bottom thereof and having a height of 50 mm or smaller, at least one antenna coil disposed around the chamber for receiving high frequency power therein, and at least one electromagnetic coil disposed around the antenna coil. The cylindrical vacuum chamber may be replaced with a plate made of a dielectric substance. The apparatus is operative to carry out photoresist using etching without leaving any residue under a high selection ratio to the photoresist. In addition, the etching product does not tend to adhere to the vacuum chamber, and it would be easy to remove etching product from the vacuum chamber, even if the product adheres to the vacuum chamber.
摘要翻译：一种用于产生等离子体的装置，包括由电介质材料制成的圆柱形真空室，该室仅在其底部开口并具有50mm或更小的高度，至少一个设置在室周围的用于在其中接收高频功率的天线线圈以及设置在天线线圈周围的至少一个电磁线圈。圆柱形真空室可以用由电介质材料制成的板代替。该设备可操作以使用蚀刻来执行光致抗蚀剂，而不会使光致抗蚀剂具有高选择比的任何残留物。此外，即使产品粘附到真空室，蚀刻产品也不会粘附到真空室，并且容易将真空室中的蚀刻产物除去。

7. 发明授权

US5792710A Method for selectively etching polycide layer 失效
标题翻译：选择性蚀刻多晶硅化物层的方法
公开(公告)号：US5792710A
公开(公告)日：1998-08-11
申请号：US814699
申请日：1997-03-11
申请人： Kazuyoshi Yoshida , Hidenobu Miyamoto , Eiji Ikawa
发明人： Kazuyoshi Yoshida , Hidenobu Miyamoto , Eiji Ikawa
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/3213
CPC分类号： H01L21/32137
摘要： Disclosed herein is a method of manufacturing a semiconductor device, the method including a step of anisotropic-etching of a high-melting-point (or refractory) metal silicide layer by use of a halogen-containing gas using. This halogen-containing gas has a boron trichloride gas as a main component gas and either one of a chlorine gas or a hydrogen bromide gas as an auxiliary or a sub-component gas.
摘要翻译：本文公开了一种制造半导体器件的方法，所述方法包括使用含卤素气体对含有高卤化物的金属硅化物层进行各向异性蚀刻的步骤。该含卤素气体具有作为主要成分气体的三氯化硼气体和作为辅助气体的氯气或溴化氢气体中的任意一种气体。

8. 发明授权

US07615498B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07615498B2
公开(公告)日：2009-11-10
申请号：US11655261
申请日：2007-01-19
申请人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
发明人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76832
摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
摘要翻译：半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210，SiO 2膜212和SiCN膜 214。第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。第二SiOC膜210的碳含量被调节为大于第一SiOC膜204的碳含量。这使得可以在保持绝缘夹层的低介电常数的同时，改善绝缘中间层与其它绝缘层的粘附性。

9. 发明授权

US07180191B2 Semiconductor device and method of manufacturing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07180191B2
公开(公告)日：2007-02-20
申请号：US11048929
申请日：2005-02-03
申请人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
发明人： Yoichi Sasaki , Koichi Ohto , Noboru Morita , Tatsuya Usami , Hidenobu Miyamoto
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76835 , H01L21/76801 , H01L21/76807 , H01L21/76832
摘要： A semiconductor device 200 comprises a SiCN film 202 formed on a semiconductor substrate (not shown), a first SiOC film 204 formed thereon, a SiCN film 208 formed thereon, a second SiOC film 210 formed thereon, a SiO2 film 212 and a SiCN film 214 formed thereon. The first SiOC film 204 has a barrier metal layer 216 and via 218 formed therein, and the second SiOC film 210 has a barrier metal layer 220 and wiring metal layer 222 formed therein. Carbon content of the second SiOC film 210 is adjusted larger than that of the first SiOC film 204. This makes it possible to improve adhesiveness of the insulating interlayer with other insulating layers, while keeping a low dielectric constant of the insulating interlayer.
摘要翻译：半导体器件200包括形成在半导体衬底（未示出）上的SiCN膜202，形成在其上的第一SiOC膜204，形成在其上的SiCN膜208，形成在其上的第二SiOC膜210， SUB>膜212和形成在其上的SiCN膜214。第一SiOC膜204具有形成在其中的阻挡金属层216和通孔218，并且第二SiOC膜210具有形成在其中的阻挡金属层220和布线金属层222。第二SiOC膜210的碳含量被调整为大于第一SiOC膜204的碳含量。这使得可以在保持绝缘中间层的低介电常数的同时提高绝缘中间层与其它绝缘层的粘附性。

10. 发明授权

US5690781A Plasma processing apparatus for manufacture of semiconductor devices 失效
标题翻译：用于制造半导体器件的等离子体处理装置
公开(公告)号：US5690781A
公开(公告)日：1997-11-25
申请号：US527847
申请日：1995-09-13
申请人： Kazuyoshi Yoshida , Hidenobu Miyamoto
发明人： Kazuyoshi Yoshida , Hidenobu Miyamoto
IPC分类号： H01L21/302 , H01J37/32 , H01L21/205 , H01L21/3065
CPC分类号： H01J37/32458 , H01J37/321
摘要： A plasma processing apparatus comprises a reaction chamber to hold a high-density plasma and having a dielectric plate window, a spiral coil placed outside the reaction chamber and close to the dielectric window, and a lower electrode which holds a wafer to be processed in place and installed in the reaction chamber facing the dielectric plate. A first radio frequency current supply to the coil, a mechanism for varying the distance between the coil and the dielectric plate window, and a second radio frequency voltage supply to the lower electrode is provided. Excellent uniformity of the ion current density of the plasma and hence etching rate is achieved by making the thickness of a central part of the dielectric plate window thicker than its peripheral parts. Also, the uniformity of the plasma and the etching rate is achieved by making the induction field produced by the coil axially symmetrical about the axial center of the reaction chamber. The etching profile and the material etching selectivity are controlled by moving the coil in the axial direction of the coil.
摘要翻译：等离子体处理装置包括用于保持高密度等离子体并具有电介质窗口的反应室，设置在反应室外部并靠近电介质窗口的螺旋线圈，以及将待处理晶片保持就位的下电极并安装在面向电介质板的反应室中。提供到线圈的第一射频电流，用于改变线圈和介质板窗口之间的距离的机构，以及向下电极提供第二射频电压源。通过使电介质平板窗口的中心部分的厚度比其周边部分厚，实现了等离子体的离子电流密度的优异的均匀性以及蚀刻速率。此外，等离子体的均匀性和蚀刻速率通过使线圈产生的感应场围绕反应室的轴心轴向对称来实现。通过沿线圈的轴向移动线圈来控制蚀刻轮廓和材料蚀刻选择性。

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