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1. 发明授权

US06995447B2 Silicon on insulator device having trench isolation layer and method for manufacturing the same 有权
公开(公告)号：US06995447B2
公开(公告)日：2006-02-07
申请号：US10810285
申请日：2004-03-26
申请人： Tae-jung Lee , Byung-sun Kim , Myoung-hwan Oh , Seung-han Yoo , Myung-sun Shin , Sang-wook Park
发明人： Tae-jung Lee , Byung-sun Kim , Myoung-hwan Oh , Seung-han Yoo , Myung-sun Shin , Sang-wook Park
IPC分类号： H10L29/00 , H10L27/01 , H10L29/76 , H10L29/40
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76283 , H01L29/78615 , H01L29/78636
摘要： A silicon-on-insulator (SOI) device and a method for manufacturing the same includes a substrate, which includes a base layer, a buried oxide layer, and a semiconductor layer, and an isolation layer which is formed in a trench that defines an active region on the semiconductor layer. The trench comprises a first region having a depth smaller than the thickness of the semiconductor layer and a second region having a depth as much as the thickness of the semiconductor layer. The isolation layer includes an oxide layer and a nitride liner that are sequentially formed along the surface of the trench and a dielectric layer that fills the trench.

2. 发明授权

US06927495B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06927495B2
公开(公告)日：2005-08-09
申请号：US10642279
申请日：2003-08-18
申请人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
发明人： Koji Arita , Masayoshi Tagami , Hidenobu Miyamoto
IPC分类号： G03F7/40 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L27/15 , H10L23/48 , H10L23/52 , H10L29/40
CPC分类号： H01L21/76811 , H01L21/76808 , H01L21/76813
摘要： Disclosed is a semiconductor device having a precision-worked dual damascene structure. A semiconductor substrate is obtained by forming at least a first interlayer film, an etching stopper film, a second interlayer film, a first hard mask and a second hard mask on a substrate in the order mentioned, the second hard mask being formed to have a trench pattern. At least a light absorbing sacrificial film, which has an etching rate different from that of a photoresist and is removable by use of a stripping solution, is formed on the semiconductor substrate in such a manner that the overall surface thereof will be flat. The photoresist is formed on the light absorbing sacrificial film and has an aperture pattern whose opening width is less than that of the trench pattern. At least the light absorbing sacrificial film, the first hard mask and the second interlayer film are etched selectively, one after the other, using the photoresist as an etching mask.
摘要翻译：公开了具有精密加工的双镶嵌结构的半导体器件。半导体衬底是通过以下述顺序在衬底上形成至少第一层间膜，蚀刻停止膜，第二层间膜，第一硬掩模和第二硬掩模而获得的，第二硬掩模形成为具有沟槽图案。至少一种具有与光致抗蚀剂不同的蚀刻速率并且可以通过使用剥离溶液去除的光吸收牺牲膜以这样的方式形成在半导体衬底上，使得其整个表面是平坦的。光致抗蚀剂形成在光吸收牺牲膜上，并且具有开口宽度小于沟槽图案的开口宽度的孔径图案。使用光致抗蚀剂作为蚀刻掩模，至少吸光牺牲膜，第一硬掩模和第二层间膜被选择性地蚀刻。

3. 发明授权

US07690551B2 Die attach by temperature gradient lead free soft solder metal sheet or film 有权
标题翻译：通过温度梯度无铅焊接金属片或薄膜贴附
公开(公告)号：US07690551B2
公开(公告)日：2010-04-06
申请号：US11027002
申请日：2004-12-31
申请人： Ong You Yang
发明人： Ong You Yang
IPC分类号： B23K35/14 , H10L29/40
CPC分类号： H01L24/27 , H01L21/6836 , H01L24/29 , H01L24/83 , H01L2221/68327 , H01L2224/274 , H01L2224/2908 , H01L2224/29101 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/83191 , H01L2224/83801 , H01L2924/01006 , H01L2924/01011 , H01L2924/01015 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/01327 , H01L2924/0133 , H01L2924/0134 , H01L2924/014 , H01L2924/0665 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/15747 , H01L2924/00 , H01L2924/01028 , H01L2924/00014
摘要： A die attach process employs a temperature gradient lead free soft solder metal sheet or thin film as the die attach material. The sheet or thin film is formed to a uniform thickness and has a heat vaporizable polymer adhesive layer on one surface, by which the thin film is laminated onto the back metal of the silicon wafer. The thin film is lead-free and composed of acceptably non-toxic materials. The thin film remains semi-molten (that is, not flowable) in reflow temperatures in the range about 260° C. to 280° C. The polymer adhesive layer is effectively vaporized at the high reflow temperatures during the die mount.
摘要翻译：芯片连接工艺采用温度梯度无铅软焊料金属片或薄膜作为芯片附着材料。片或薄膜形成均匀的厚度，并且在一个表面上具有可热蒸发的聚合物粘合剂层，通过该薄膜将薄膜层压到硅晶片的背金属上。该薄膜是无铅的，由可接受的无毒材料组成。薄膜在约260℃至280℃的范围内的回流温度下保持半熔融（即不可流动）。聚合物粘合剂层在模具安装期间以高回流温度有效地蒸发。

4. 发明授权

US06873059B2 Semiconductor package with metal foil attachment film 有权
标题翻译：半导体封装带金属箔贴膜
公开(公告)号：US06873059B2
公开(公告)日：2005-03-29
申请号：US10008049
申请日：2001-11-13
申请人： Masazumi Amagai , Akira Karashima
发明人： Masazumi Amagai , Akira Karashima
IPC分类号： H01L21/58 , H01L21/68 , H01L23/31 , H01L23/498 , H10L29/40
CPC分类号： H01L21/6836 , H01L23/3114 , H01L23/4985 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L2221/68327 , H01L2224/05599 , H01L2224/274 , H01L2224/29 , H01L2224/29101 , H01L2224/2919 , H01L2224/29298 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83191 , H01L2224/8385 , H01L2224/85399 , H01L2224/92247 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/3512 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device comprising a semiconductor chip having an active and a passive surface, the passive surface adhesively attached to a substrate film by means of a multilayer composite; this composite comprising a metal foil having first and second surfaces and an adhesive layer attached on each of these surfaces. The multilayer composite has an average modulus larger than the modulus of the encapsulating molding compound used in the semiconductor device. By applying the composite to assembling face-up chip-scale devices, stress in solder joints is reduced and solder fatigue life enhanced.
摘要翻译：一种半导体器件，包括具有有源和无源表面的半导体芯片，所述被动表面借助于多层复合材料粘附到基底膜上; 该复合材料包括具有第一表面和第二表面的金属箔，以及粘合层附着在这些表面的每一个上。多层复合材料的平均模量大于在半导体器件中使用的封装模塑料的模量。通过将复合材料应用于面朝上的芯片级装置，焊接点的应力降低，焊料疲劳寿命提高。

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