专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07476610B2 Removable spacer 有权
标题翻译：可拆卸垫片
公开(公告)号：US07476610B2
公开(公告)日：2009-01-13
申请号：US11598242
申请日：2006-11-10
申请人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
发明人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
IPC分类号： H01L21/44
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.
摘要翻译：提供了一种用于形成半导体器件的方法。栅极堆叠形成在衬底的表面上。提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相聚合物在基材的表面上并且形成沉积材料的轮廓。使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。去除聚合物间隔物。

2. 发明申请

US20080111166A1 Removable spacer 有权
标题翻译：可拆卸垫片
公开(公告)号：US20080111166A1
公开(公告)日：2008-05-15
申请号：US11598242
申请日：2006-11-10
申请人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
发明人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.
摘要翻译：提供了一种用于形成半导体器件的方法。栅极堆叠形成在衬底的表面上。提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相聚合物在基材的表面上并且形成沉积材料的轮廓。使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。去除聚合物间隔物。

3. 发明授权

US07390749B2 Self-aligned pitch reduction 有权
标题翻译：自对准螺距减小
公开(公告)号：US07390749B2
公开(公告)日：2008-06-24
申请号：US11558238
申请日：2006-11-09
申请人： Ji Soo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.
摘要翻译：提供了一种用于在具有存储区域和周边区域的蚀刻层中提供特征的方法。存储器图案化掩模形成在第一牺牲层上。第一组牺牲层特征被蚀刻到第一牺牲层和第二牺牲层中。第一组牺牲层特征的特征填充有填充材料。第一牺牲层被去除。这些空间随着收缩侧壁沉积而收缩。第二组牺牲层特征被蚀刻到第二牺牲层中。去除填充材料和收缩侧壁沉积。在存储器区域和外围区域上形成周边图案化掩模。通过外围图案化掩模蚀刻第二牺牲层。去除周边图案掩模。特征从第二牺牲层蚀刻到蚀刻层中。

4. 发明授权

US07910489B2 Infinitely selective photoresist mask etch 有权
标题翻译：无限选择性光刻胶掩模蚀刻
公开(公告)号：US07910489B2
公开(公告)日：2011-03-22
申请号：US11357548
申请日：2006-02-17
申请人： Ji Soo Kim , Peter Cirigliano , Sangheon Lee , Dongho Heo , Daehan Choi , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Peter Cirigliano , Sangheon Lee , Dongho Heo , Daehan Choi , S. M. Reza Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/30655
摘要： A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.
摘要翻译：提供了一种用于将特征蚀刻到设置在光刻胶掩模下方而不具有中间硬掩模的蚀刻层中的方法。提供多个蚀刻循环。每个蚀刻循环包括提供沉积蚀刻阶段，其将特征蚀刻到蚀刻层中并将聚合物沉积在特征的侧壁上并在光致抗蚀剂上方，并提供去除沉积在侧壁上的聚合物的清洁相。

5. 发明授权

US07098130B1 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US07098130B1
公开(公告)日：2006-08-29
申请号：US11016304
申请日：2004-12-16
申请人： Ji Soo Kim , Sangheon Lee , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , S. M. Reza Sadjadi
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： A method for forming dual damascene features in a dielectric layer. Vias are partially etched in the dielectric layer. A trench pattern mask is formed over the dielectric layer. Trenches are partially etched in the dielectric layer. The trench pattern mask is stripped. The dielectric layer is further etched to complete etch the vias and the trenches in the dielectric layer.
摘要翻译：一种在介电层中形成双镶嵌特征的方法。在电介质层中部分地蚀刻通孔。在电介质层上形成沟槽图案掩模。在介电层中部分蚀刻沟槽。剥去沟槽图案掩模。进一步蚀刻电介质层以完成蚀刻介电层中的通路和沟槽。

6. 发明申请

US20090121324A1 ETCH WITH STRIATION CONTROL 审中-公开
标题翻译： ETCH与测度控制
公开(公告)号：US20090121324A1
公开(公告)日：2009-05-14
申请号：US12349142
申请日：2009-01-06
申请人： S. M. Reza Sadjadi , Peter Cirigliano , Ji Soo Kim , Zhisong Huang , Eric A. Hudson
发明人： S. M. Reza Sadjadi , Peter Cirigliano , Ji Soo Kim , Zhisong Huang , Eric A. Hudson
IPC分类号： C23F1/08 , H01L29/00
CPC分类号： H01L21/0273 , H01L21/0274 , H01L21/31144 , H01L21/76802 , Y10S438/942 , Y10S438/949
摘要： A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.
摘要翻译：提供了蚀刻蚀刻层中的特征的方法。在具有侧壁的光致抗蚀剂特征的蚀刻层上形成图案化的光致抗蚀剂掩模，其中光致抗蚀剂特征的侧壁具有形成峰和谷的条纹。光致抗蚀剂特征的侧壁的条纹减小。减小条纹包括至少一个周期，其中每个周期包括蚀刻由光致抗蚀剂特征的侧壁的条纹形成的峰，并沉积在光致抗蚀剂特征的侧壁上。通过光致抗蚀剂特征将特征蚀刻到蚀刻层中。去除光致抗蚀剂掩模。

7. 发明授权

US07772122B2 Sidewall forming processes 有权
标题翻译：侧壁成型工艺
公开(公告)号：US07772122B2
公开(公告)日：2010-08-10
申请号：US12233517
申请日：2008-09-18
申请人： Peter Cirigliano , Helen Zhu , Ji Soo Kim , S. M. Reza Sadjadi
发明人： Peter Cirigliano , Helen Zhu , Ji Soo Kim , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/31144 , H01L21/312
摘要： An etch layer underlying a patterned photoresist mask is provided. A plurality of sidewall forming processes are performed. Each sidewall forming process comprises depositing a protective layer on the patterned photoresist mask by performing multiple cyclical depositions. Each cyclical deposition involves at least a depositing phase for depositing a deposition layer over surfaces of the patterned photoresist mask and a profile shaping phase for shaping vertical surfaces in the deposition layer. Each sidewall forming process further comprises a breakthrough etch for selectively etching horizontal surfaces of the protective layer with respect to vertical surfaces of the protective layer. Afterwards, the etch layer is etched to form a feature having a critical dimension that is less than the critical dimension of the features in the patterned photoresist mask.
摘要翻译：提供了图案化光刻胶掩模下面的蚀刻层。执行多个侧壁形成工序。每个侧壁形成工艺包括通过执行多个循环沉积在图案化的光致抗蚀剂掩模上沉积保护层。每个循环沉积涉及至少沉积阶段，用于在图案化的光致抗蚀剂掩模的表面上沉积沉积层，以及用于在沉积层中形成垂直表面的轮廓成形阶段。每个侧壁形成工艺还包括用于相对于保护层的垂直表面选择性地蚀刻保护层的水平表面的穿透蚀刻。之后，刻蚀蚀刻层以形成临界尺寸小于图案化光致抗蚀剂掩模中特征的临界尺寸的特征。

8. 发明授权

US07491647B2 Etch with striation control 失效
标题翻译：蚀刻与条纹控制
公开(公告)号：US07491647B2
公开(公告)日：2009-02-17
申请号：US11223363
申请日：2005-09-09
申请人： S. M. Reza Sadjadi , Peter Cirigliano , Ji Soo Kim , Zhisong Huang , Eric A. Hudson
发明人： S. M. Reza Sadjadi , Peter Cirigliano , Ji Soo Kim , Zhisong Huang , Eric A. Hudson
IPC分类号： H01L21/311
CPC分类号： H01L21/0273 , H01L21/0274 , H01L21/31144 , H01L21/76802 , Y10S438/942 , Y10S438/949
摘要： A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed.
摘要翻译：提供了蚀刻蚀刻层中的特征的方法。在具有侧壁的光致抗蚀剂特征的蚀刻层上形成图案化的光致抗蚀剂掩模，其中光致抗蚀剂特征的侧壁具有形成峰和谷的条纹。光致抗蚀剂特征的侧壁的条纹减小。减小条纹包括至少一个周期，其中每个周期包括蚀刻由光致抗蚀剂特征的侧壁的条纹形成的峰，并沉积在光致抗蚀剂特征的侧壁上。通过光致抗蚀剂特征将特征蚀刻到蚀刻层中。去除光致抗蚀剂掩模。

9. 发明申请

US20080146032A1 GLUE LAYER FOR HYDROFLUOROCARBON ETCH 有权
标题翻译：石油醚水合物
公开(公告)号：US20080146032A1
公开(公告)日：2008-06-19
申请号：US11610953
申请日：2006-12-14
申请人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Deepak K. Gupta , S. M. Reza Sadjadi
IPC分类号： H01L21/3105
CPC分类号： H01L21/31144 , H01L21/30655 , H01L21/31116 , H01L21/312
摘要： A method for etching features in an etch layer disposed below a mask on a process wafer is provided. A hydrocarbon based glue layer is deposited. The etch layer on the process wafer is etched with at least one cycle, wherein each cycle comprises depositing a hydrofluorocarbon layer over the mask and on the hydrocarbon based glue layer, wherein the hydrocarbon based glue layer increases adhesion of the hydrofluorocarbon layer and etching the etch layer.
摘要翻译：提供了一种用于蚀刻设置在处理晶片上的掩模下方的蚀刻层中的特征的方法。沉积烃基胶层。用至少一个循环蚀刻处理晶片上的蚀刻层，其中每个循环包括在掩模上和基于烃的胶层上沉积氢氟烃层，其中基于烃的胶层增加氢氟烃层的粘附和蚀刻蚀刻层。

10. 发明授权

US07084070B1 Treatment for corrosion in substrate processing 有权
标题翻译：处理基板加工腐蚀
公开(公告)号：US07084070B1
公开(公告)日：2006-08-01
申请号：US10623016
申请日：2003-07-17
申请人： Sangheon Lee , Sean S. Kang , S M Reza Sadjadi , Subhash Deshmukh , Ji Soo Kim
发明人： Sangheon Lee , Sean S. Kang , S M Reza Sadjadi , Subhash Deshmukh , Ji Soo Kim
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/31111 , H01L21/31116 , H01L21/32137 , H01L21/32138 , H01L21/76807 , H01L21/7681 , H01L21/76814
摘要： A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH3COOH) or acetic acid/ammonium hydroxide (NH4OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H2 plasma. BTA passivation may be optionally performed on the substrate.
摘要翻译：公开了一种用于处理基板以形成半导体器件的方法。衬底包括设置在金属层上方的蚀刻停止层。该方法包括使用利用含氯蚀刻剂源气体的等离子体蚀刻工艺将蚀刻停止层蚀刻到铜金属层下方，从而在蚀刻停止层中形成蚀刻停止层开口。蚀刻停止层包括SiN和SiC材料中的至少一种。此后，该方法包括使用含有乙酸（CH 3 COOH）或乙酸/氢氧化铵（NH 4 OH）的溶液对底物进行湿处理至去除至少一些铜氧化物。或者，可以使用H 2 O 3等离子体去除铜氧化物。可以任选地在衬底上进行BTA钝化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式