专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07390749B2 Self-aligned pitch reduction 有权
标题翻译：自对准螺距减小
公开(公告)号：US07390749B2
公开(公告)日：2008-06-24
申请号：US11558238
申请日：2006-11-09
申请人： Ji Soo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.
摘要翻译：提供了一种用于在具有存储区域和周边区域的蚀刻层中提供特征的方法。存储器图案化掩模形成在第一牺牲层上。第一组牺牲层特征被蚀刻到第一牺牲层和第二牺牲层中。第一组牺牲层特征的特征填充有填充材料。第一牺牲层被去除。这些空间随着收缩侧壁沉积而收缩。第二组牺牲层特征被蚀刻到第二牺牲层中。去除填充材料和收缩侧壁沉积。在存储器区域和外围区域上形成周边图案化掩模。通过外围图案化掩模蚀刻第二牺牲层。去除周边图案掩模。特征从第二牺牲层蚀刻到蚀刻层中。

2. 发明授权

US07910489B2 Infinitely selective photoresist mask etch 有权
标题翻译：无限选择性光刻胶掩模蚀刻
公开(公告)号：US07910489B2
公开(公告)日：2011-03-22
申请号：US11357548
申请日：2006-02-17
申请人： Ji Soo Kim , Peter Cirigliano , Sangheon Lee , Dongho Heo , Daehan Choi , S. M. Reza Sadjadi
发明人： Ji Soo Kim , Peter Cirigliano , Sangheon Lee , Dongho Heo , Daehan Choi , S. M. Reza Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/30655
摘要： A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.
摘要翻译：提供了一种用于将特征蚀刻到设置在光刻胶掩模下方而不具有中间硬掩模的蚀刻层中的方法。提供多个蚀刻循环。每个蚀刻循环包括提供沉积蚀刻阶段，其将特征蚀刻到蚀刻层中并将聚合物沉积在特征的侧壁上并在光致抗蚀剂上方，并提供去除沉积在侧壁上的聚合物的清洁相。

3. 发明授权

US07476610B2 Removable spacer 有权
标题翻译：可拆卸垫片
公开(公告)号：US07476610B2
公开(公告)日：2009-01-13
申请号：US11598242
申请日：2006-11-10
申请人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
发明人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
IPC分类号： H01L21/44
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.
摘要翻译：提供了一种用于形成半导体器件的方法。栅极堆叠形成在衬底的表面上。提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相聚合物在基材的表面上并且形成沉积材料的轮廓。使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。去除聚合物间隔物。

4. 发明申请

US20080111166A1 Removable spacer 有权
标题翻译：可拆卸垫片
公开(公告)号：US20080111166A1
公开(公告)日：2008-05-15
申请号：US11598242
申请日：2006-11-10
申请人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
发明人： Ji Soo Kim , Conan Chiang , Daehan Choi , S. M. Reza Sadjadi , Michael Goss
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method for forming semiconductor devices is provided. A gate stack is formed over a surface of a substrate. A plurality of cycles for forming polymer spacers on sides of the gate stack is provided, where each cycle comprises providing a deposition phase that deposits material on the sides of the polymer spacer and over the surface of the substrate, and providing a cleaning phase that removes polymer over the surface of the substrate and shapes a profile of the deposited material. Dopant is implanted into the substrate using the polymer spacers as a dopant mask. The polymer spacers are removed.
摘要翻译：提供了一种用于形成半导体器件的方法。栅极堆叠形成在衬底的表面上。提供了用于在栅极叠层的侧面上形成聚合物间隔物的多个循环，其中每个循环包括提供沉积相，其沉积材料在聚合物间隔物的侧面上并在基底的表面上，并提供清除相聚合物在基材的表面上并且形成沉积材料的轮廓。使用聚合物间隔物作为掺杂剂掩模将掺杂剂注入到衬底中。去除聚合物间隔物。

5. 发明授权

US07560388B2 Self-aligned pitch reduction 有权
标题翻译：自对准螺距减小
公开(公告)号：US07560388B2
公开(公告)日：2009-07-14
申请号：US11291303
申请日：2005-11-30
申请人： Jisoo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
发明人： Jisoo Kim , Sangheon Lee , Daehan Choi , S. M. Reza Sadjadi
IPC分类号： H01L21/311
CPC分类号： H01L21/0338
摘要： A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了一种在电介质层中提供特征的方法。在电介质层上形成牺牲层。一组牺牲层特征被蚀刻到牺牲层中。通过牺牲层将介电层特征的第一组蚀刻到介电层中。第一组介电层特征和一组牺牲层特征用填充材料填充。牺牲层被去除。填充材料的各部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将第二组介电层特征蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

6. 发明申请

US20070193973A1 Infinitely selective photoresist mask etch 有权
标题翻译：无限选择性光刻胶掩模蚀刻
公开(公告)号：US20070193973A1
公开(公告)日：2007-08-23
申请号：US11357548
申请日：2006-02-17
申请人： Ji Kim , Peter Cirigliano , Sangheon Lee , Dongho Heo , Daehan Choi , S. Sadjadi
发明人： Ji Kim , Peter Cirigliano , Sangheon Lee , Dongho Heo , Daehan Choi , S. Sadjadi
IPC分类号： C23F1/00 , C03C15/00
CPC分类号： H01L21/31116 , H01L21/30655
摘要： A method for etching features into an etch layer disposed below a photoresist mask without an intermediate hardmask is provided. A plurality of etch cycles are provided. Each etch cycle comprises providing a deposition etch phase that etches features into the etch layer and deposits polymer on sidewalls of the features and over the photoresist and providing a cleaning phase that removes polymer deposited on the sidewalls.
摘要翻译：提供了一种用于将特征蚀刻到设置在光刻胶掩模下方而不具有中间硬掩模的蚀刻层中的方法。提供多个蚀刻循环。每个蚀刻循环包括提供沉积蚀刻阶段，其将特征蚀刻到蚀刻层中并将聚合物沉积在特征的侧壁上并在光致抗蚀剂上方，并提供去除沉积在侧壁上的聚合物的清洁相。

7. 发明申请

US20070123053A1 Self-aligned pitch reduction 有权
标题翻译：自对准螺距减小
公开(公告)号：US20070123053A1
公开(公告)日：2007-05-31
申请号：US11291303
申请日：2005-11-30
申请人： Jisoo Kim , Sangheon Lee , Daehan Choi , S.M. Sadjadi
发明人： Jisoo Kim , Sangheon Lee , Daehan Choi , S.M. Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/0338
摘要： A method providing features in a dielectric layer is provided. A sacrificial layer is formed over the dielectric layer. A set of sacrificial layer features is etched into the sacrificial layer. A first set of dielectric layer features is etched into the dielectric layer through the sacrificial layer. The first set of dielectric layer features and the set of sacrificial layer features are filled with a filler material. The sacrificial layer is removed. The widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. A second set of dielectric layer features is etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed.
摘要翻译：提供了一种在电介质层中提供特征的方法。在电介质层上形成牺牲层。一组牺牲层特征被蚀刻到牺牲层中。通过牺牲层将介电层特征的第一组蚀刻到介电层中。第一组介电层特征和一组牺牲层特征用填充材料填充。牺牲层被去除。填充材料的各部分之间的间隙的宽度随收缩侧壁沉积而收缩。通过收缩侧壁沉积将第二组介电层特征蚀刻到介电层中。去除填充材料和收缩侧壁沉积。

8. 发明申请

US20070122977A1 SELF-ALIGNED PITCH REDUCTION 有权
标题翻译：自对准减法
公开(公告)号：US20070122977A1
公开(公告)日：2007-05-31
申请号：US11558238
申请日：2006-11-09
申请人： Ji Kim , Sangheon Lee , Daehan Choi , S. Sadjadi
发明人： Ji Kim , Sangheon Lee , Daehan Choi , S. Sadjadi
IPC分类号： H01L21/336
CPC分类号： H01L21/0338 , H01L21/0337 , H01L21/31144
摘要： A method for providing features in an etch layer with a memory region and a peripheral region is provided. A memory patterned mask is formed over a first sacrificial layer. A first set of sacrificial layer features is etched into the first sacrificial layer and a second sacrificial layer. Features of the first set of sacrificial layer features are filled with filler material. The first sacrificial layer is removed. The spaces are shrunk with a shrink sidewall deposition. A second set of sacrificial layer features is etched into the second sacrificial layer. The filler material and shrink sidewall deposition are removed. A peripheral patterned mask is formed over the memory region and peripheral region. The second sacrificial layer is etched through the peripheral patterned mask. The peripheral patterned mask is removed. Features are etched into the etch layer from the second sacrificial layer.
摘要翻译：提供了一种用于在具有存储区域和周边区域的蚀刻层中提供特征的方法。存储器图案化掩模形成在第一牺牲层上。第一组牺牲层特征被蚀刻到第一牺牲层和第二牺牲层中。第一组牺牲层特征的特征填充有填充材料。第一牺牲层被去除。这些空间随着收缩侧壁沉积而收缩。第二组牺牲层特征被蚀刻到第二牺牲层中。去除填充材料和收缩侧壁沉积。在存储器区域和外围区域上形成周边图案化掩模。通过外围图案化掩模蚀刻第二牺牲层。去除周边图案掩模。特征从第二牺牲层蚀刻到蚀刻层中。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式