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1. 发明授权

US07084070B1 Treatment for corrosion in substrate processing 有权
标题翻译：处理基板加工腐蚀
公开(公告)号：US07084070B1
公开(公告)日：2006-08-01
申请号：US10623016
申请日：2003-07-17
申请人： Sangheon Lee , Sean S. Kang , S M Reza Sadjadi , Subhash Deshmukh , Ji Soo Kim
发明人： Sangheon Lee , Sean S. Kang , S M Reza Sadjadi , Subhash Deshmukh , Ji Soo Kim
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/76802 , H01L21/31111 , H01L21/31116 , H01L21/32137 , H01L21/32138 , H01L21/76807 , H01L21/7681 , H01L21/76814
摘要： A method for processing substrate to form a semiconductor device is disclosed. The substrate includes an etch stop layer disposed above a metal layer. The method includes etching through the etch stop layer down to the copper metal layer, using a plasma etch process that utilizes a chlorine-containing etchant source gas, thereby forming etch stop layer openings in the etch stop layer. The etch stop layer includes at least one of a SiN and SiC material. Thereafter, the method includes performing a wet treatment on the substrate using a solution that contains acetic acid (CH3COOH) or acetic acid/ammonium hydroxide (NH4OH) to remove at least some of the copper oxides. Alternatively, the copper oxides may be removed using a H2 plasma. BTA passivation may be optionally performed on the substrate.
摘要翻译：公开了一种用于处理基板以形成半导体器件的方法。衬底包括设置在金属层上方的蚀刻停止层。该方法包括使用利用含氯蚀刻剂源气体的等离子体蚀刻工艺将蚀刻停止层蚀刻到铜金属层下方，从而在蚀刻停止层中形成蚀刻停止层开口。蚀刻停止层包括SiN和SiC材料中的至少一种。此后，该方法包括使用含有乙酸（CH 3 COOH）或乙酸/氢氧化铵（NH 4 OH）的溶液对底物进行湿处理至去除至少一些铜氧化物。或者，可以使用H 2 O 3等离子体去除铜氧化物。可以任选地在衬底上进行BTA钝化。

2. 发明授权

US07541291B2 Reduction of feature critical dimensions 有权
标题翻译：减少功能关键尺寸
公开(公告)号：US07541291B2
公开(公告)日：2009-06-02
申请号：US11821422
申请日：2007-06-22
申请人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , S. M. Reza Sadjadi , Gan Ming Zhao
发明人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , S. M. Reza Sadjadi , Gan Ming Zhao
IPC分类号： H01L21/302
CPC分类号： H01L21/76802 , H01L21/0337 , H01L21/31116 , H01L21/31144 , H01L21/76816
摘要： A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.
摘要翻译：提供了一个图层中的一个特征。在该层上形成光致抗蚀剂层。光致抗蚀剂层被图案化以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征，其中光致抗蚀剂特征具有第一临界尺寸。在光致抗蚀剂特征的侧壁上沉积保形层以减少光致抗蚀剂特征的临界尺寸。将特征蚀刻到层中，其中层特征具有小于第一临界尺寸的第二临界尺寸。

3. 发明授权

US07250371B2 Reduction of feature critical dimensions 有权
标题翻译：减少功能关键尺寸
公开(公告)号：US07250371B2
公开(公告)日：2007-07-31
申请号：US10648953
申请日：2003-08-26
申请人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , S. M. Reza Sadjadi , Gan Ming Zhao
发明人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , S. M. Reza Sadjadi , Gan Ming Zhao
IPC分类号： H01L21/311
CPC分类号： H01L21/76802 , H01L21/0337 , H01L21/31116 , H01L21/31144 , H01L21/76816
摘要： A feature in a layer is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls, where the photoresist features have a first critical dimension. A conformal layer is deposited over the sidewalls of the photoresist features to reduce the critical dimensions of the photoresist features. Features are etched into the layer, wherein the layer features have a second critical dimension, which is less than the first critical dimension.
摘要翻译：提供了一个图层中的一个特征。在该层上形成光致抗蚀剂层。光致抗蚀剂层被图案化以形成具有光致抗蚀剂侧壁的光致抗蚀剂特征，其中光致抗蚀剂特征具有第一临界尺寸。在光致抗蚀剂特征的侧壁上沉积保形层以减少光致抗蚀剂特征的临界尺寸。将特征蚀刻到层中，其中层特征具有小于第一临界尺寸的第二临界尺寸。

4. 发明授权

US06969685B1 Etching a dielectric layer in an integrated circuit structure having a metal hard mask layer 有权
标题翻译：在具有金属硬掩模层的集成电路结构中蚀刻介电层
公开(公告)号：US06969685B1
公开(公告)日：2005-11-29
申请号：US10246926
申请日：2002-09-18
申请人： SiYi Li , S. M. Reza Sadjadi , Sean S. Kang
发明人： SiYi Li , S. M. Reza Sadjadi , Sean S. Kang
IPC分类号： H01L21/302 , H01L21/311 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/32136
摘要： The invention relates to the etching of a dielectric layer in an integrated circuit (IC) structure having a patterned metal hard mask layer. The method comprises feeding a gas mixture that includes a carbon monoxide (CO) and at least one fluorocarbon gas mixture into a reactor. The gas mixture has no oxygen (O2) gas. The gas mixture is then converted into a plasma. The plasma selectively etches the dielectric layer. Typically, the dielectric layer comprises silicon.
摘要翻译：本发明涉及具有图案化金属硬掩模层的集成电路（IC）结构中的介电层的蚀刻。该方法包括将包含一氧化碳（CO）和至少一种碳氟化合物气体混合物的气体混合物进料到反应器中。气体混合物没有氧（O 2/2）气体。然后将气体混合物转化成等离子体。等离子体选择性地蚀刻介电层。通常，电介质层包括硅。

5. 发明授权

US06919278B2 Method for etching silicon carbide 有权
标题翻译：腐蚀碳化硅的方法
公开(公告)号：US06919278B2
公开(公告)日：2005-07-19
申请号：US10199190
申请日：2002-07-19
申请人： Sean S. Kang , Si Yi Li , S. M. Reza Sadjadi
发明人： Sean S. Kang , Si Yi Li , S. M. Reza Sadjadi
IPC分类号： H01J37/00 , H01L21/04 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/461 , H01L21/768
CPC分类号： H01L21/3065 , H01L21/31116 , H01L21/32137
摘要： A system and method for achieving a silicon carbide to low-k dielectric etch selectivity ratio of greater than 1:1 using a chlorine containing gas and either hydrogen (H2) gas or nitrogen (N2) gas is described. The method is applied to a semiconductor substrate having a low-k dielectric layer and a silicon carbide layer. The chlorine containing gas is a gas mixture that includes either HCl, BCl3, Cl2, or any combination thereof. In one embodiment, the method provides for supplying an etchant gas comprising a chlorine containing gas and a hydrogen (H2) gas. The etchant gas is then energized to generate a plasma which then etches openings in the silicon carbide at a faster etch rate than the low-k dielectric etch rate. In an alternative embodiment, the etchant gas mixture comprises a chlorine containing gas and a nitrogen (N2) gas.
摘要翻译：一种用于使用含氯气体和氢气（H 2/2）气体或氮气（N 2）的气体来实现碳化硅至低k电介质蚀刻选择比大于1:1的系统和方法， 2气体）。该方法应用于具有低k电介质层和碳化硅层的半导体衬底。含氯气体是包含HCl，BCl 3，Cl 2 H 2或其任何组合的气体混合物。在一个实施方案中，该方法提供了供应包含含氯气体和氢气（H 2 H 2）气体的蚀刻剂气体。然后将蚀刻剂气体通电以产生等离子体，然后等离子体以比低k电介质蚀刻速率更快的蚀刻速率蚀刻碳化硅中的开口。在替代实施例中，蚀刻剂气体混合物包括含氯气体和氮气（N 2/2）气体。

6. 发明授权

US07192531B1 In-situ plug fill 有权
标题翻译：现场插头填充
公开(公告)号：US07192531B1
公开(公告)日：2007-03-20
申请号：US10603412
申请日：2003-06-24
申请人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , Reza Sadjadi
发明人： Sean S. Kang , Sangheon Lee , Wan-Lin Chen , Eric A. Hudson , Reza Sadjadi
IPC分类号： H01L21/302
CPC分类号： H01L21/76808 , H01L21/31138
摘要： A method for forming damascene features in a dielectric layer over a barrier layer over a substrate is provided. A plurality of vias are etched in the dielectric layer to the barrier layer with a plasma etching process in the plasma processing chamber. A patterned photoresist layer is formed with a trench pattern. Within a single plasma process chamber a combination via plug deposition to form plugs in the vias over the barrier layer and trench etch is provided.
摘要翻译：提供了一种用于在衬底上的阻挡层上的介电层中形成镶嵌特征的方法。在等离子体处理室中通过等离子体蚀刻工艺将多个通孔在电介质层中蚀刻到阻挡层。形成具有沟槽图案的图案化的光致抗蚀剂层。在单个等离子体处理室内，提供了通过插塞沉积的组合以在阻挡层上的通孔中形成插塞和沟槽蚀刻。

7. 发明授权

US08987139B2 Method of patterning a low-k dielectric film 有权
标题翻译：图案化低k电介质膜的方法
公开(公告)号：US08987139B2
公开(公告)日：2015-03-24
申请号：US14159832
申请日：2014-01-21
申请人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311 , H01L21/321 , H01L21/3213
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/321 , H01L21/32136 , H01L21/76802
摘要： Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实施例中，在一个实施例中，图案化低k电介质膜的方法涉及在低k电介质层上形成和图案化金属氮化物掩模层。低k电介质层设置在衬底之上。该方法还涉及通过用基于O 2 / N 2 / SixFy的等离子体处理钝化金属氮化物掩模层。该方法还涉及蚀刻低k电介质层的一部分。

8. 发明申请

US20080044995A1 Trilayer resist organic layer etch 有权
标题翻译：三层抗蚀剂有机层蚀刻
公开(公告)号：US20080044995A1
公开(公告)日：2008-02-21
申请号：US11507862
申请日：2006-08-21
申请人： Sean S. Kang , Sang Jun Cho , Tom Choi , Taejoon Han
发明人： Sean S. Kang , Sang Jun Cho , Tom Choi , Taejoon Han
IPC分类号： H01L21/44
CPC分类号： H01L21/76808
摘要： A method of forming dual damascene features in a porous low-k dielectric layer is provided. Vias are formed in the porous low-k dielectric layer. An organic planarization layer is formed over the porous low-k dielectric layer, wherein the organic layer fills the vias. A photoresist mask is formed over the organic planarization layer. Features are etched into the organic planarization layer comprising providing a CO2 containing etch gas and forming a plasma from the CO2 containing etch gas, which etches the organic planarization layer. Trenches are etched into the porous low-k dielectric layer using the organic planarization layer as a mask. The organic planarization layer is stripped.
摘要翻译：提供了一种在多孔低k电介质层中形成双镶嵌特征的方法。在多孔低k电介质层中形成通孔。在多孔低k电介质层上形成有机平坦化层，其中有机层填充通孔。在有机平坦化层上形成光致抗蚀剂掩模。特征被蚀刻到有机平坦化层中，包括提供含有CO 2的蚀刻气体，并从含有CO 2 2的蚀刻气体形成等离子体，其蚀刻有机平坦化层。使用有机平坦化层作为掩模将沟槽蚀刻到多孔低k电介质层中。剥离有机平坦化层。

9. 发明授权

US09006106B2 Method of removing a metal hardmask 有权
标题翻译：去除金属硬掩模的方法
公开(公告)号：US09006106B2
公开(公告)日：2015-04-14
申请号：US13889550
申请日：2013-05-08
申请人： Chia-Ling Kao , Kwang-soo Kim , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Kwang-soo Kim , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/02063 , H01L21/31116 , H01L21/32136 , H01L21/76811 , H01L21/76813 , H01L21/76814 , H01L2221/1063
摘要： Methods of removing metal hardmasks in the presence of ultra low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film includes forming a pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. The method also includes etching, using the metal nitride hardmask layer as a mask, the pattern at least partially into the low-k dielectric film, the etching involving using a plasma etch based on SiFx. The etching also involves forming an SiOx passivation layer at least on sidewalls of the low-k dielectric film formed during the etching. The method also includes removing the metal nitride hardmask layer by a dry etch process, where the SiOx passivation layer protects the low-k dielectric film during the removing.
摘要翻译：描述了在超低k电介质膜存在下去除金属硬掩模的方法。在一个示例中，图案化低k电介质膜的方法包括在形成在衬底上方的低k电介质膜上形成的金属氮化物硬掩模层中形成图案。该方法还包括使用金属氮化物硬掩模层作为掩模的蚀刻，该图案至少部分地进入低k电介质膜，该蚀刻涉及使用基于SiFx的等离子体蚀刻。蚀刻还包括至少在蚀刻期间形成的低k电介质膜的侧壁上形成SiO x钝化层。该方法还包括通过干蚀刻工艺去除金属氮化物硬掩模层，其中SiO x钝化层在去除期间保护低k绝缘膜。

10. 发明申请

US20140213060A1 METHOD OF PATTERNING A LOW-K DIELECTRIC FILM 有权
标题翻译：绘制低K电介质膜的方法
公开(公告)号：US20140213060A1
公开(公告)日：2014-07-31
申请号：US14159832
申请日：2014-01-21
申请人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
发明人： Chia-Ling Kao , Sean S. Kang , Srinivas D. Nemani
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/321 , H01L21/32136 , H01L21/76802
摘要： Methods of patterning low-k dielectric films are described. In an example, In an embodiment, a method of patterning a low-k dielectric film involves forming and patterning a metal nitride mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves passivating the metal nitride mask layer by treating with a plasma based on O2/N2/SixFy. The method also involves etching a portion of the low-k dielectric layer.
摘要翻译：描述了低k介电膜图案的方法。在一个实施例中，在一个实施例中，图案化低k电介质膜的方法涉及在低k电介质层上形成和图案化金属氮化物掩模层。低k电介质层设置在衬底之上。该方法还涉及通过用基于O 2 / N 2 / SixFy的等离子体处理钝化金属氮化物掩模层。该方法还涉及蚀刻低k电介质层的一部分。

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