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1. 发明授权

US07362554B2 Electrostatic discharge (ESD) clamp using output driver 失效
标题翻译：使用输出驱动器的静电放电（ESD）钳位
公开(公告)号：US07362554B2
公开(公告)日：2008-04-22
申请号：US10431942
申请日：2003-05-08
申请人： James Dub Austin , Kenneth W. Fernald
发明人： James Dub Austin , Kenneth W. Fernald
IPC分类号： H02H3/22
CPC分类号： H01L27/0285
摘要： Electrostatic discharge (ESD) clamp using output driver. An electrostatic discharge (ESD) protection device for an output driver having a p-channel transistor and n-transistor pair connected between a power supply terminal and ground for driving an input/output pad therefrom. An ESD event detector is provided for detecting an ESD event on the pad. A drive circuit drives the n-channel and p-channel drive transistors in response to receiving a logic control signal to either drive the pad from the supply terminal or to sink the pad to ground. ESD protection logic circuitry is provided to cause both the p-channel and n-channel transistors to turn on when the ESD event detector detects an ESD event, the ESD protection circuitry disposed forward of the drive circuit such that the ESD protection logic circuitry operates independent of the state of the drive circuit.
摘要翻译：使用输出驱动器的静电放电（ESD）钳位。一种用于输出驱动器的静电放电（ESD）保护装置，其具有连接在电源端子和地之间的p沟道晶体管和n型晶体管对，用于驱动输入/输出衬垫。提供ESD事件检测器，用于检测焊盘上的ESD事件。驱动电路响应于接收到逻辑控制信号而驱动n沟道和p沟道驱动晶体管，以从供电端驱动焊盘或将焊盘吸收到地。提供ESD保护逻辑电路以在ESD事件检测器检测到ESD事件时使p沟道晶体管和n沟道晶体管导通，ESD保护电路设置在驱动电路的前方，使得ESD保护逻辑电路独立运行的驱动电路的状态。

2. 发明授权

US08914624B2 Changing the reset state of a processor 有权
标题翻译：更改处理器的复位状态
公开(公告)号：US08914624B2
公开(公告)日：2014-12-16
申请号：US12976263
申请日：2010-12-22
申请人： Kenneth W. Fernald , Paul I. Zavalney
发明人： Kenneth W. Fernald , Paul I. Zavalney
IPC分类号： G06F1/24 , G06F13/00 , G06F9/44 , G06F9/30
CPC分类号： G06F13/00 , G06F1/24 , G06F9/24 , G06F9/30 , G06F9/44 , G06F9/4403
摘要： An apparatus includes a memory, a processor and a controller. The processor is adapted to begin executing instructions based on content stored starting at a predetermined address in the memory upon reset of the processor. The controller is adapted to, in response to the reset of the processor, provide to the processor content for the predetermined address other than the content that is stored starting at the predetermined address.
摘要翻译：一种装置包括存储器，处理器和控制器。处理器适于在处理器复位时，基于存储器中预定地址开始存储的内容开始执行指令。控制器适于响应于处理器的复位，向除了从预定地址开始存储的内容之外的预定地址提供给处理器内容。

3. 发明授权

US08638081B2 Active droop current sharing 有权
标题翻译：主动下垂电流共享
公开(公告)号：US08638081B2
公开(公告)日：2014-01-28
申请号：US13526791
申请日：2012-06-19
申请人： Douglas E. Heineman , Kenneth W. Fernald
发明人： Douglas E. Heineman , Kenneth W. Fernald
IPC分类号： H02J7/34
CPC分类号： H02M3/1584 , G06F1/26 , H02J1/08 , H02M2001/008 , Y10T307/422
摘要： Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.
摘要翻译：负载点（POL）调节器可以配置为多相POL DC-DC（直流到直流电）转换器，以多相配置运行，以提高系统可用的总电流。可以通过利用使用匹配的人造线路电阻（下降电阻）的有源低带宽电流共享算法同时在稳态和动态瞬态状态期间保持多环路稳定性来执行电流平衡。可以通过设备之间的数字通信来促进当前共享算法，其中数字总线可以是单线总线，并行总线或时钟和数据总线。

4. 发明申请

US20130321183A1 CODER WITH SNOOP MODE 有权
标题翻译：编码器与SNOOP模式
公开(公告)号：US20130321183A1
公开(公告)日：2013-12-05
申请号：US13485711
申请日：2012-05-31
申请人： Kenneth W. Fernald
发明人： Kenneth W. Fernald
IPC分类号： H03M13/00
CPC分类号： G06F13/4027 , H03M13/09
摘要： Techniques are disclosed relating to coding data in an apparatus. In one embodiment, the apparatus includes a coder circuit coupled to a data bus, where the coder circuit is configured to receive an indication that data is being transmitted over the data bus from a first circuit to a second circuit. The coder circuit is configured to perform a coding operation on the data in response to receiving the indication. In some embodiments, the coder circuit is configured to operate in a mode in which the coder circuit captures data of a data transmission via the data bus without being specified as a participant of the data transmission. When the coder circuit is not operating in the mode, the coder circuit is not configured to capture data of a data transmission without being specified as a participant of the data transmission.
摘要翻译：公开了与装置中的编码数据有关的技术。在一个实施例中，该装置包括耦合到数据总线的编码器电路，其中编码器电路被配置为接收数据正在数据总线上从第一电路传输到第二电路的指示。编码器电路被配置为响应于接收到指示而对数据执行编码操作。在一些实施例中，编码器电路被配置为在编码器电路经由数据总线捕获数据传输的数据而不被指定为数据传输的参与者的模式下操作。当编码器电路不在该模式下操作时，编码器电路不被配置为捕获数据传输的数据而不被指定为数据传输的参与者。

5. 发明申请

US20120262141A1 Active Droop Current Sharing 有权
标题翻译：主动下垂电流共享
公开(公告)号：US20120262141A1
公开(公告)日：2012-10-18
申请号：US13526791
申请日：2012-06-19
申请人： Douglas E. Heineman , Kenneth W. Fernald
发明人： Douglas E. Heineman , Kenneth W. Fernald
IPC分类号： G05F1/46
CPC分类号： H02M3/1584 , G06F1/26 , H02J1/08 , H02M2001/008 , Y10T307/422
摘要： Point-of-load (POL) regulators may be configured as multiphase POL DC-to-DC (direct current to direct current) converters, operating in a multiphase configuration in order to boost the total current available to a system. Current balancing may be performed by utilizing an active low bandwidth current sharing algorithm that uses matched artificial line resistance (droop resistance) while maintaining multi-loop stability during both steady-state and dynamic transient states. The current sharing algorithm may be facilitated through digital communication between the devices, where the digital bus may be a single wire bus, a parallel bus or a clock-and-data bus.
摘要翻译：负载点（POL）调节器可以配置为多相POL DC-DC（直流到直流电）转换器，以多相配置运行，以提高系统可用的总电流。可以通过利用使用匹配的人造线路电阻（下降电阻）的有源低带宽电流共享算法同时在稳态和动态瞬态状态期间保持多环路稳定性来执行电流平衡。可以通过设备之间的数字通信来促进当前共享算法，其中数字总线可以是单线总线，并行总线或时钟和数据总线。

6. 发明申请

US20100325325A1 Integrated Multi-Function Point-Of-Load Regulator Circuit 有权
标题翻译：集成多功能点负载调节器电路
公开(公告)号：US20100325325A1
公开(公告)日：2010-12-23
申请号：US12868973
申请日：2010-08-26
申请人： Kenneth W. Fernald , James W. Templeton , John A. Wishneusky
发明人： Kenneth W. Fernald , James W. Templeton , John A. Wishneusky
IPC分类号： G06F13/42 , G06F1/26 , G06F13/00
CPC分类号： G06F1/26 , H02M3/1584
摘要： A power management system may comprise two or more POL regulators configured to transmit and receive data over a shared bus according to either a proprietary or a common bus protocol. Each POL regulator may be identified by a unique address that is part of an address group, and may be configured via pin strapping to be able to perform a variety of power management functions. Any one of the POL regulators within the address group may become a bus master and transmit information to the shared bus by addressing itself The other POL regulators in the address group may monitor the shared bus for events, and may respond to the transmitted information according to their address, their configuration, and the transmitted information. The response may include the POL regulators performing one or more power management functions, including adjusting their respective output voltages. The POL regulators may respond to each event according to the requirements corresponding to the event, thereby performing the necessary tasks to enable power management functions without the need for interconnecting analog signal lines and without being explicitly controlled.
摘要翻译：功率管理系统可以包括两个或更多个POL调节器，其被配置为根据专有或公共总线协议通过共享总线发送和接收数据。每个POL调节器可以由作为地址组的一部分的唯一地址来识别，并且可以通过引脚捆绑来配置以能够执行各种功率管理功能。地址组中的任何一个POL调节器可以成为总线主机，并通过寻址本身将信息发送到共享总线地址组中的其他POL调节器可以监视事件的共享总线，并且可以根据他们的地址，他们的配置和传输的信息。响应可以包括执行一个或多个功率管理功能的POL调节器，包括调整它们各自的输出电压。 POL调节器可以根据与该事件相对应的要求对每个事件进行响应，由此执行必要的任务以实现功率管理功能，而不需要互连模拟信号线并且不被明确控制。

7. 发明授权

US07256611B2 Cross-bar matrix with LCD functionality 失效
标题翻译：带有LCD功能的横杆矩阵
公开(公告)号：US07256611B2
公开(公告)日：2007-08-14
申请号：US11005700
申请日：2004-12-07
申请人： Douglas R. Holberg , Kenneth W. Fernald
发明人： Douglas R. Holberg , Kenneth W. Fernald
IPC分类号： H03K19/177
CPC分类号： H03K19/1731
摘要： A cross-bar matrix includes a plurality of matrix cells arranged in rows and columns wherein each row of cells is associated with a signal input and each column of cells is associated with a common signal output. An enable input controls whether at least a portion of the cells couple a signal on the associated common signal input to a signal output associated with a cell or couple an LCD signal to a signal output and exclude control of the at least portion of said plurality of cells by the control input.
摘要翻译：交叉矩阵矩阵包括以行和列排列的多个矩阵单元，其中每行单元与信号输入相关联，并且每列单元与公共信号输出相关联。使能输入控制是否至少一部分单元将相关联的公共信号输入上的信号耦合到与单元相关联的信号输出或将LCD信号耦合到信号输出，并且排除对所述多个单元由控制输入。

8. 发明授权

US07119527B2 Voltage reference circuit using PTAT voltage 有权
公开(公告)号：US07119527B2
公开(公告)日：2006-10-10
申请号：US10880915
申请日：2004-06-30
申请人： Kenneth W. Fernald
发明人： Kenneth W. Fernald
IPC分类号： G05F3/16 , G05F1/10 , H02J1/10
CPC分类号： G05F3/262
摘要： A voltage reference generator is disclosed that includes a current generator for generating a current that is proportional to absolute temperature (PTAT), the current generator having an internal resistance. This provides a PTAT current that is proportional to the resistance and wherein the temperature coefficient of the PTAT current is defined by the resistance. An output node is driven by the current generator with the PTAT current. A stack of serial connected MOS devices is connected between the output voltage and a ground reference voltage. The stack of transistors has a transimpedance associated therewith which has a temperature coefficient that is opposite in polarity to the temperature coefficient of the internal resistance and of a magnitude to provide a voltage on the output node that is substantially stable over temperature.

9. 发明授权

US06839795B1 Priority cross-bar decoder 有权
标题翻译：优先交叉条解码器
公开(公告)号：US06839795B1
公开(公告)日：2005-01-04
申请号：US09584308
申请日：2000-05-31
申请人： Kenneth W. Fernald , Danny J. Allred , Donald E. Alfano
发明人： Kenneth W. Fernald , Danny J. Allred , Donald E. Alfano
IPC分类号： H04Q3/52 , G06F13/00
CPC分类号： H04Q3/52 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/1325
摘要： A matrix of routing cells forming a cross-bar decoder (70). Signal triplets (84, 86, 88) coupled to the cross-bar decoder (70) are assigned a priority. A register (50) provide outputs to the cross-bar decoder (70) to either activate or deactivate routing of the triplet signals (84, 86,88) through the cross-bar decoder (70). The routing cells (72-82) are arranged in a matrix of columns and rows, where the triplet signals are applied to the row routing cells (72, 74, 76) and are extracted at the column routing cells (76, 80, 82). When a routing cell in a row is enabled to couple signals to an output, it disables all other lower priority routing cells in its column so that they cannot route signals to that output. Based on the automatic disabling of routing cells by others, the signals ripple through the cross-bar decoder (70) until all high priority I/O pins are used. The outputs of the cross-bar decoder (70) are coupled to respective I/O pins (170, 172, 174) by way of respective driver circuits (212, 216, 236).
摘要翻译：形成交叉条形码解码器（70）的路由信元的矩阵。耦合到交叉条形码解码器（70）的信号三元组（84,86,88）被赋予优先权。寄存器（50）向交叉条形码解码器（70）提供输出以通过交叉条形码解码器（70）来激活或去激活三联信号（84,88,88）的路由。路由单元（72-82）被布置成列和行的矩阵，其中三元组信号被施加到行路由单元（72,74,76），并且在列路由单元（76,80,82）处被提取）。当一行中的路由单元被使能以将信号耦合到输出时，它将禁用其列中的所有其他较低优先级的路由单元，使得它们不能将信号路由到该输出。基于其他路由单元的自动禁用，通过交叉条形码解码器（70）的信号直到所有高优先级I / O引脚使用。横杆解码器（70）的输出通过相应的驱动器电路（212,216,236）耦合到相应的I / O引脚（170,172,174）。

10. 发明申请

US20130212408A1 REGULATING A CLOCK FREQUENCY OF A PERIPHERAL 审中-公开
标题翻译：调节外围时钟频率
公开(公告)号：US20130212408A1
公开(公告)日：2013-08-15
申请号：US13369667
申请日：2012-02-09
申请人： Kenneth W. Fernald
发明人： Kenneth W. Fernald
IPC分类号： G06F1/00
CPC分类号： G06F1/324 , Y02D10/126
摘要： A method of communicating in an electronic system or apparatus is disclosed. The method includes using a processor to communicate with a peripheral. The processor has a power state. The method also includes regulating a clock frequency of the peripheral, where this regulation is based at least in part on the power state of the processor.
摘要翻译：公开了一种在电子系统或装置中通信的方法。该方法包括使用处理器与外围设备进行通信。处理器具有电源状态。该方法还包括调节外设的时钟频率，其中该调节至少部分地基于处理器的功率状态。

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