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1. 发明授权

US07954007B2 Detecting faulty CPU heat sink coupling during system power-up 失效
标题翻译：在系统上电期间检测CPU散热器耦合故障
公开(公告)号：US07954007B2
公开(公告)日：2011-05-31
申请号：US11551961
申请日：2006-10-23
申请人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
发明人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
IPC分类号： G06F11/00
CPC分类号： H01L23/34 , G06F1/206 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.
摘要翻译：本发明涉及在系统上电期间检测故障的CPU散热器耦合。根据本发明的实施例的方法包括：从初始系统上电监视CPU温度上升的斜率; 确定CPU温度上升的斜率是否超过预期值; 并且在CPU温度升高的斜率超过预期值的情况下，指示与耦合到CPU的散热器相关的可能故障（PFA）的存在。

2. 发明申请

US20080154536A1 DETECTING FAULTY CPU HEAT SINK COUPLING DURING SYSTEM POWER-UP 失效
标题翻译：在系统加电期间检测故障CPU散热耦合
公开(公告)号：US20080154536A1
公开(公告)日：2008-06-26
申请号：US11551961
申请日：2006-10-23
申请人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
发明人： Henry G. McMillan , Christopher C. Moody , Challis L. Purrington , Terry L. Sawyers , Michael L. Scollard , Richard P. Southers , Troy S. Voytko , Christopher C. West , Christopher L. Wood
IPC分类号： G06F15/00
CPC分类号： H01L23/34 , G06F1/206 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to the detection of faulty CPU heat sink coupling during system power-up. A method in accordance with an embodiment of the present invention includes: monitoring a slope of a CPU temperature rise from initial system power-up; determining if the slope of the CPU temperature rise exceeds an expected value; and in the case that the slope of the CPU temperature rise exceeds the expected value, indicating an existence of a possible fault (PFA) related to a heat sink coupled to the CPU.
摘要翻译：本发明涉及在系统上电期间检测故障的CPU散热器耦合。根据本发明的实施例的方法包括：从初始系统上电监视CPU温度上升的斜率; 确定CPU温度上升的斜率是否超过预期值; 并且在CPU温度升高的斜率超过预期值的情况下，指示与耦合到CPU的散热器相关的可能故障（PFA）的存在。

3. 发明授权

US07992030B2 Fall time accelerator circuit 有权
标题翻译：下降时间加速器电路
公开(公告)号：US07992030B2
公开(公告)日：2011-08-02
申请号：US11746102
申请日：2007-05-09
申请人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
发明人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
IPC分类号： G06F1/00
CPC分类号： H03K5/1534 , H03K19/01721
摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
摘要翻译：本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

4. 发明申请

US20080278207A1 FALL TIME ACCELERATOR CIRCUIT 有权
标题翻译：落地时间加速器电路
公开(公告)号：US20080278207A1
公开(公告)日：2008-11-13
申请号：US11746102
申请日：2007-05-09
申请人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
发明人： Henry G. McMillan , Pravin Patel , Challis L. Purrington , Gwendolyn R. Tobin , Christopher C. West , Ivan R. Zapata
IPC分类号： H03K5/12
CPC分类号： H03K5/1534 , H03K19/01721
摘要： Embodiments of the invention address deficiencies of the art in respect to digital signal transmissions and provide a novel and non-obvious fall time accelerator circuit for use in a USB interface. In one embodiment of the invention, the USB interface can include a USB port driver coupled to a host controller driver over a USB bus. The USB interface also can include a fall time accelerator circuit coupled to the USB bus between the USB port driver and the host controller driver. The fall time accelerator circuit can include a pulse signal generator coupled to an inbound signal path from the USB bus and arranged to generate a tunable pulse upon detecting a falling edge of a digital signal on the inbound signal path. The circuit further can include an active timer additionally coupled to the inbound signal path to hold the tunable pulse for a set period of time. Finally, the circuit can include a falling drive signal strengthener coupled to an outbound signal path from the pulse signal generator arranged to release the tunable pulse on the outbound signal path onto the USB bus.
摘要翻译：本发明的实施例解决了与数字信号传输相关的技术缺陷，并且提供了一种用于USB接口的新颖且不可见的下降时间加速器电路。在本发明的一个实施例中，USB接口可以包括通过USB总线耦合到主控制器驱动器的USB端口驱动器。 USB接口还可以包括在USB端口驱动器和主机控制器驱动器之间耦合到USB总线的下降时间加速器电路。下降时间加速器电路可以包括耦合到来自USB总线的入站信号路径的脉冲信号发生器，并且被布置成在检测入站信号路径上的数字信号的下降沿时产生可调脉冲。电路还可以包括另外耦合到入站信号路径的有源定时器，以将可调谐脉冲保持一段时间。最后，电路可以包括耦合到来自脉冲信号发生器的出站信号路径的下降驱动信号加强器，该脉冲信号发生器布置成将出站信号路径上的可调谐脉冲释放到USB总线上。

5. 发明授权

US07667980B2 Printed circuit boards for countering signal distortion 有权
标题翻译：打印信号失真的电路板
公开(公告)号：US07667980B2
公开(公告)日：2010-02-23
申请号：US11539990
申请日：2006-10-10
申请人： Brian A. Baker , James E. Hughes , Thomas D. Pahel, Jr. , Pravin Patel , Challis L. Purrington , Christopher C. West
发明人： Brian A. Baker , James E. Hughes , Thomas D. Pahel, Jr. , Pravin Patel , Challis L. Purrington , Christopher C. West
IPC分类号： H05K7/00
CPC分类号： H05K1/0216 , H05K1/0231 , H05K1/0233 , H05K3/429 , H05K2201/0792 , H05K2201/09318 , H05K2201/09627 , H05K2201/09781 , H05K2201/1003
摘要： Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.
摘要翻译：公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

6. 发明申请

US20080084679A1 Printed Circuit Boards for Countering Signal Distortion 有权
标题翻译：用于对抗信号失真的印刷电路板
公开(公告)号：US20080084679A1
公开(公告)日：2008-04-10
申请号：US11539990
申请日：2006-10-10
申请人： Brian A. Baker , James E. Hughes , Thomas D. Pahel , Pravin Patel , Challis L. Purrington , Christopher C. West
发明人： Brian A. Baker , James E. Hughes , Thomas D. Pahel , Pravin Patel , Challis L. Purrington , Christopher C. West
IPC分类号： H05K7/00
CPC分类号： H05K1/0216 , H05K1/0231 , H05K1/0233 , H05K3/429 , H05K2201/0792 , H05K2201/09318 , H05K2201/09627 , H05K2201/09781 , H05K2201/1003
摘要： Printed circuit boards for countering signal distortion are disclosed that include: a conductive pathway on a printed circuit board between a transmitter and a receiver, the conductive pathway comprised of traces and vias connected together for conductive transfer of a signal from the transmitter to the receiver; a parasitic element on the printed circuit board, the parasitic element having a parasitic effect that distorts the signal; and one or more passive elements mounted adjacent to the conductive pathway without connecting to the conductive pathway, the passive elements having a corrective effect to reduce the distortion from the parasitic effect on the signal.
摘要翻译：公开了用于对抗信号失真的印刷电路板，其包括：在发射器和接收器之间的印刷电路板上的导电路径，由连接在一起的迹线和通孔组成的导电通路，用于将信号从发射器传导到接收器; 在印刷电路板上的寄生元件，寄生元件具有扭曲信号的寄生效应; 以及一个或多个无源元件安装在导电路径附近而不连接到导电路径，无源元件具有校正效果，以减少由信号引起的寄生效应的失真。

7. 发明申请

US20090219835A1 Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes 有权
标题翻译：优化多个计算节点之间的物理数据通信拓扑
公开(公告)号：US20090219835A1
公开(公告)日：2009-09-03
申请号：US12040316
申请日：2008-02-29
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： H04L12/28
CPC分类号： H04L41/0823 , H04L12/462 , H04L41/08 , H04L41/085 , H04L41/12 , H04L47/10
摘要： Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.
摘要翻译：公开了用于优化多个计算节点之间的物理数据通信拓扑的方法，装置和产品，所述物理数据通信拓扑包括被配置为连接用于数据通信的多个节点的物理链路，其包括以预定速度反复进行：通过物理数据通信拓扑中的每对节点之间的链路检测网络数据包，每个网络分组的特征在于一个或多个分组属性; 根据该网络分组的分组属性向每个网络分组分配分组权重; 根据分配给在该对节点之间传送的网络分组的分组权重，为物理数据通信拓扑中的每对节点确定节点对业务权重; 并且根据节点对业务权重重新配置每对节点之间的物理链路。

8. 发明授权

US07394281B1 Bi-directional universal serial bus booster circuit 失效
标题翻译：双向通用串行总线升压电路
公开(公告)号：US07394281B1
公开(公告)日：2008-07-01
申请号：US12023659
申请日：2008-01-31
申请人： Justin P. Bandholz , Moises Cases , Bradley D. Herman , Erdem Matoglu , Bhyrav M. Mutnury , Thomas D. Pahel , Pravin S. Patel , Nam H. Pham , Christopher C. West
发明人： Justin P. Bandholz , Moises Cases , Bradley D. Herman , Erdem Matoglu , Bhyrav M. Mutnury , Thomas D. Pahel , Pravin S. Patel , Nam H. Pham , Christopher C. West
IPC分类号： H03K17/16
CPC分类号： G06F13/4072
摘要： A bi-directional universal serial bus (“USB”) circuit for boosting a signal on a USB bus disclosed. The circuit includes a first stage inverting buffer coupled to a second stage inverting buffer to form a non-inverting buffer circuit. A high pass filter is coupled in series with the non-inverting buffer circuit to provide AC coupling to the USB bus and to allow fast signal edges through the circuit. The booster circuit is arranged to improve signal quality over a USB bus to allow additional USB devices and longer USB busses to be utilized.
摘要翻译：一种用于升高USB总线上的信号的双向通用串行总线（“USB”）电路。电路包括耦合到第二级反相缓冲器以形成非反相缓冲电路的第一级反相缓冲器。高通滤波器与非反相缓冲电路串联耦合以提供与USB总线的AC耦合并允许通过电路的快速信号边缘。升压电路被设置为通过USB总线提高信号质量，以允许使用附加的USB设备和更长的USB总线。

9. 发明申请

US20090083529A1 Memory Switching Data Processing System 有权
标题翻译：内存切换数据处理系统
公开(公告)号：US20090083529A1
公开(公告)日：2009-03-26
申请号：US11859835
申请日：2007-09-24
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
摘要翻译：一种包括一个或多个中央处理单元（“CPU”）的存储器切换数据处理系统; 组织在至少两组存储器模块中的随机存取存储器; 一个或多个存储器总线为CPU和存储器模块之间的数据提供通信路径; 以及灵活可配置的存储器总线开关，其包括将第一CPU适配到第一存储器模块组的第一配置，以及将第二CPU适配到第二存储器模块组，以及将第一CPU适配到第一存储器模块组的第二配置;以及第二组内存模块。

10. 发明申请

US20090083472A1 DESIGN STRUCTURE FOR A MEMORY SWITCHING DATA PROCESSING SYSTEM 有权
标题翻译：一种存储器切换数据处理系统的设计结构
公开(公告)号：US20090083472A1
公开(公告)日：2009-03-26
申请号：US12114992
申请日：2008-05-05
申请人： JUSTIN P. BANDHOLZ , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： JUSTIN P. BANDHOLZ , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F13/00
CPC分类号： G11C29/56 , G06F13/1652 , G11C29/025 , G11C29/028 , G11C29/50008
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
摘要翻译：提供了一种体现在用于设计，制造和/或测试存储器切换数据处理系统的机器可读存储介质中的设计结构。存储器切换数据处理系统包括一个或多个中央处理单元（“CPU”）; 组织在至少两组存储器模块中的随机存取存储器; 一个或多个存储器总线为CPU和存储器模块之间的数据提供通信路径; 以及灵活可配置的存储器总线开关，其包括将第一CPU适配到第一存储器模块组的第一配置，以及将第二CPU适配到第二存储器模块组，以及将第一CPU适配到第一存储器模块组的第二配置;以及第二组内存模块。

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