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1. 发明申请

US20120213066A1 Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes 有权
标题翻译：优化多个计算节点之间的物理数据通信拓扑
公开(公告)号：US20120213066A1
公开(公告)日：2012-08-23
申请号：US13461309
申请日：2012-05-01
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： H04L12/24 , H04L12/56
CPC分类号： H04L41/0823 , H04L12/462 , H04L41/08 , H04L41/085 , H04L41/12 , H04L47/10
摘要： Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.
摘要翻译：公开了用于优化多个计算节点之间的物理数据通信拓扑的方法，装置和产品，所述物理数据通信拓扑包括被配置为连接用于数据通信的多个节点的物理链路，其包括以预定速度反复进行：通过物理数据通信拓扑中的每对节点之间的链路检测网络数据包，每个网络分组的特征在于一个或多个分组属性; 根据该网络分组的分组属性向每个网络分组分配分组权重; 根据分配给在该对节点之间传送的网络分组的分组权重，为物理数据通信拓扑中的每对节点确定节点对业务权重; 并且根据节点对业务权重重新配置每对节点之间的物理链路。

2. 发明授权

US08213334B2 Optimizing a physical data communications topology between a plurality of computing nodes 有权
标题翻译：优化多个计算节点之间的物理数据通信拓扑
公开(公告)号：US08213334B2
公开(公告)日：2012-07-03
申请号：US12040316
申请日：2008-02-29
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： H04L12/28 , H04L1/00 , G01R31/08 , G06F11/00 , G06F15/173 , G08C15/00 , H04J1/16 , H04J3/14
CPC分类号： H04L41/0823 , H04L12/462 , H04L41/08 , H04L41/085 , H04L41/12 , H04L47/10
摘要： Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.
摘要翻译：公开了用于优化多个计算节点之间的物理数据通信拓扑的方法，装置和产品，所述物理数据通信拓扑包括被配置为连接用于数据通信的多个节点的物理链路，其包括以预定速度反复进行：通过物理数据通信拓扑中的每对节点之间的链路检测网络数据包，每个网络分组的特征在于一个或多个分组属性; 根据该网络分组的分组属性向每个网络分组分配分组权重; 根据分配给在该对节点之间传送的网络分组的分组权重，为物理数据通信拓扑中的每对节点确定节点对业务权重; 并且根据节点对业务权重重新配置每对节点之间的物理链路。

3. 发明申请

US20090219835A1 Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes 有权
标题翻译：优化多个计算节点之间的物理数据通信拓扑
公开(公告)号：US20090219835A1
公开(公告)日：2009-09-03
申请号：US12040316
申请日：2008-02-29
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： H04L12/28
CPC分类号： H04L41/0823 , H04L12/462 , H04L41/08 , H04L41/085 , H04L41/12 , H04L47/10
摘要： Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.
摘要翻译：公开了用于优化多个计算节点之间的物理数据通信拓扑的方法，装置和产品，所述物理数据通信拓扑包括被配置为连接用于数据通信的多个节点的物理链路，其包括以预定速度反复进行：通过物理数据通信拓扑中的每对节点之间的链路检测网络数据包，每个网络分组的特征在于一个或多个分组属性; 根据该网络分组的分组属性向每个网络分组分配分组权重; 根据分配给在该对节点之间传送的网络分组的分组权重，为物理数据通信拓扑中的每对节点确定节点对业务权重; 并且根据节点对业务权重重新配置每对节点之间的物理链路。

4. 发明授权

US07937537B2 Memory switching data processing system 有权
标题翻译：存储器切换数据处理系统
公开(公告)号：US07937537B2
公开(公告)日：2011-05-03
申请号：US11859835
申请日：2007-09-24
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F15/16
摘要： A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
摘要翻译：一种包括一个或多个中央处理单元（“CPU”）的存储器切换数据处理系统; 组织在至少两组存储器模块中的随机存取存储器; 一个或多个存储器总线为CPU和存储器模块之间的数据提供通信路径; 以及灵活可配置的存储器总线开关，其包括将第一CPU适配到第一存储器模块组的第一配置，以及将第二CPU适配到第二存储器模块组，以及将第一CPU适配到第一存储器模块组的第二配置;以及第二组内存模块。

5. 发明申请

US20090281761A1 Detecting An Increase In Thermal Resistance Of A Heat Sink In A Computer System 有权
标题翻译：检测计算机系统中散热器的热阻增加
公开(公告)号：US20090281761A1
公开(公告)日：2009-11-12
申请号：US12118158
申请日：2008-05-09
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G01K1/02
CPC分类号： G06F11/30
摘要： Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.
摘要翻译：用于检测计算机系统中的散热器的热阻增加的方法，装置和产品，所述散热器耗散计算机系统的部件的热量，所述计算机系统包括控制穿过所述散热器的气流的风扇，所述计算机系统还包括温度监测装置，包括：通过监测模块在计算机系统运行期间使用温度监测装置测量散热片的热阻; 确定散热器的测量热阻是否大于阈值热阻，存储在非易失性存储器中的热分布中的阈值热阻，以及如果所测得的散热片的热阻大于阈值热阻通知系统管理员。

6. 发明授权

US07945740B2 Structure for a memory switching data processing system 有权
标题翻译：存储器切换数据处理系统的结构
公开(公告)号：US07945740B2
公开(公告)日：2011-05-17
申请号：US12114992
申请日：2008-05-05
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G11C29/56 , G06F13/1652 , G11C29/025 , G11C29/028 , G11C29/50008
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
摘要翻译：提供了一种体现在用于设计，制造和/或测试存储器切换数据处理系统的机器可读存储介质中的设计结构。存储器切换数据处理系统包括一个或多个中央处理单元（“CPU”）; 组织在至少两组存储器模块中的随机存取存储器; 一个或多个存储器总线为CPU和存储器模块之间的数据提供通信路径; 以及灵活可配置的存储器总线开关，其包括将第一CPU适配到第一存储器模块组的第一配置，以及将第二CPU适配到第二存储器模块组，以及将第一CPU适配到第一存储器模块组的第二配置;以及第二组内存模块。

7. 发明申请

US20090083529A1 Memory Switching Data Processing System 有权
标题翻译：内存切换数据处理系统
公开(公告)号：US20090083529A1
公开(公告)日：2009-03-26
申请号：US11859835
申请日：2007-09-24
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F15/177
CPC分类号： G06F15/16
摘要： A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
摘要翻译：一种包括一个或多个中央处理单元（“CPU”）的存储器切换数据处理系统; 组织在至少两组存储器模块中的随机存取存储器; 一个或多个存储器总线为CPU和存储器模块之间的数据提供通信路径; 以及灵活可配置的存储器总线开关，其包括将第一CPU适配到第一存储器模块组的第一配置，以及将第二CPU适配到第二存储器模块组，以及将第一CPU适配到第一存储器模块组的第二配置;以及第二组内存模块。

8. 发明申请

US20090083472A1 DESIGN STRUCTURE FOR A MEMORY SWITCHING DATA PROCESSING SYSTEM 有权
标题翻译：一种存储器切换数据处理系统的设计结构
公开(公告)号：US20090083472A1
公开(公告)日：2009-03-26
申请号：US12114992
申请日：2008-05-05
申请人： JUSTIN P. BANDHOLZ , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： JUSTIN P. BANDHOLZ , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S.D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F13/00
CPC分类号： G11C29/56 , G06F13/1652 , G11C29/025 , G11C29/028 , G11C29/50008
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.
摘要翻译：提供了一种体现在用于设计，制造和/或测试存储器切换数据处理系统的机器可读存储介质中的设计结构。存储器切换数据处理系统包括一个或多个中央处理单元（“CPU”）; 组织在至少两组存储器模块中的随机存取存储器; 一个或多个存储器总线为CPU和存储器模块之间的数据提供通信路径; 以及灵活可配置的存储器总线开关，其包括将第一CPU适配到第一存储器模块组的第一配置，以及将第二CPU适配到第二存储器模块组，以及将第一CPU适配到第一存储器模块组的第二配置;以及第二组内存模块。

9. 发明授权

US07962306B2 Detecting an increase in thermal resistance of a heat sink in a computer system 有权
标题翻译：检测计算机系统中散热器的热阻增加
公开(公告)号：US07962306B2
公开(公告)日：2011-06-14
申请号：US12118158
申请日：2008-05-09
申请人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Zachary B. Durham , Clifton E. Kerr , Joseph E. Maxwell , Kevin M. Reinberg , Kevin S. D. Vernon , Philip L. Weinstein , Christopher C. West
IPC分类号： G01K1/02
CPC分类号： G06F11/30
摘要： Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.
摘要翻译：用于检测计算机系统中的散热器的热阻增加的方法，装置和产品，所述散热器耗散计算机系统的部件的热量，所述计算机系统包括控制穿过所述散热器的气流的风扇，所述计算机系统还包括温度监测装置，包括：通过监测模块在计算机系统运行期间使用温度监测装置测量散热片的热阻; 确定散热器的测量热阻是否大于阈值热阻，存储在非易失性存储器中的热分布中的阈值热阻，以及如果所测得的散热片的热阻大于阈值热阻通知系统管理员。

10. 发明申请

US20090019211A1 Establishing A Redundant Array Of Inexpensive Drives 审中-公开
标题翻译：建立廉价驱动器的冗余阵列
公开(公告)号：US20090019211A1
公开(公告)日：2009-01-15
申请号：US11777691
申请日：2007-07-13
申请人： Justin P. Bandholz , Kevin M. Reinberg , Philip L. Weinstein , Christopher C. West
发明人： Justin P. Bandholz , Kevin M. Reinberg , Philip L. Weinstein , Christopher C. West
IPC分类号： G06F12/00
CPC分类号： G06F3/0632 , G06F3/0607 , G06F3/0688
摘要： Establishing, with a USB RAID controller connected to a USB hub and with USB mass storage devices connected to the USB hub and the USB RAID controller through USB connectors, the USB hub controlled by a USB host controller, a RAID array including enumerating, by the USB host controller, the USB mass storage devices, including discovering the USB RAID controller; receiving, by the USB RAID controller from a RAID console application program, an instruction to designate USB connectors as RAIDable USB connectors, the instruction including selected USB connectors; designating, by the USB RAID controller, the selected USB connectors as RAIDable USB connectors; enumerating by the USB RAID controller the USB mass storage devices connected to the RAIDable USB connectors; configuring by the USB RAID controller a RAID array, the RAID array including the USB mass storage devices; and storing, through the USB RAID controller, computer data on the RAID array.
摘要翻译：建立一个连接到USB集线器的USB RAID控制器和通过USB接口连接到USB集线器和USB RAID控制器的USB大容量存储设备，由USB主机控制器控制的USB集线器，包括枚举的RAID阵列，由 USB主机控制器，USB大容量存储设备，包括发现USB RAID控制器; 由USB RAID控制器从RAID控制台应用程序接收将USB连接器指定为可RAID式USB连接器的指令，该指令包括选定的USB连接器; 通过USB RAID控制器将选定的USB连接器指定为可RAIDable USB连接器; 通过USB RAID控制器枚举连接到RAIDable USB连接器的USB大容量存储设备; 通过USB RAID控制器配置RAID阵列，RAID阵列包括USB大容量存储设备; 并通过USB RAID控制器存储RAID阵列上的计算机数据。

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