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1. 发明专利

JPH07152461A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07152461A
公开(公告)日：1995-06-16
申请号：JP30193293
申请日：1993-12-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISODA MASANORI , TANAKA HITOSHI , ETO JUN , AOKI MASAKAZU
IPC分类号： G11C11/401 , G06F3/00 , G11C11/407 , G11C11/409
摘要： PURPOSE:To prevent the characteristic impedance of a transmission line from being lowered by reducing diffusing layer capacity parasitic on an input/output pin by reducing the gate width of an MOS transistor consisting of an output buffer. CONSTITUTION:An output circuit is composed of an output buffer OB and a driving circuit HD and their voltage sources are individually defined as Vh, V1, Vhp and V1n. The output buffer OB is a circuit serially connecting a pMOST Q1 and an nMOST Q2, and the driving circuit HD is the similar serial circuit as well. A voltage between the gates and sources of Q1 and Q2 is increased so as to reduce the gate width without decreasing a current ITT to flow to the Q1 and Q2. Namely, since the driving ability of the MOST is increased by setting the amplitude of the driving signal of the output buffer OB larger than the power supply voltage of the output buffer OB, when letting the same current flow, its gate width can be reduced. Therefore, the diffusing layer capacity to be the drain of the MOST is reduced, and the parasitic capacity of the input / output pin can be reduced.

2. 发明专利

JPH03235288A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03235288A
公开(公告)日：1991-10-21
申请号：JP2855990
申请日：1990-02-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISODA MASANORI , ETO JUN , HORIGUCHI SHINJI , AOKI MASAKAZU , WATANABE YASUSHI , ITO KIYOO
IPC分类号： G11C11/407
摘要： PURPOSE:To reduce the dispersion of operation of operation speed between chips and to accelerate a system by measuring the operating speed or a power supply voltage for each chip and changing the power supply voltage in the chip based on the result of this measurement. CONSTITUTION:The operating speed of a circuit is monitored by directly measuring the operation of a memory circuit 40. A bonding pad 50 is provided for inputted the address signal of a memory, and a bonding pad 60 is provided for outputting the data of the memory. From the input of the address signal to the output of the data, the operating speed speed of the memory is measured. According to the measured result, the power supply voltage in the chip 10 is controlled by using a power supply voltage control means 30, and the operating speed of the memory is made same as the target value. Thus, the dispersion of the operating speed between the memory chips can be reduced. Therefore, the system can be easily designed and accelerated as well.

3. 发明专利

JPH03214669A SEMICONDUCTOR STORAGE DEVICE AND REDUNDANT MEMORY REPAIR METHOD 失效
公开(公告)号：JPH03214669A
公开(公告)日：1991-09-19
申请号：JP6584089
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/41 , G11C11/401 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain a high speed and also a large storage capacity by disposing peripheral circuits in cross areas formed of a longitudinal central part and a lateral central part and by disposing memory arrays in four regions divided by the cross areas. CONSTITUTION:In a semiconductor chip or in each of areas divided by the longitudinal center line thereof, peripheral circuits are disposed in cross areas A to E formed of the longitudinal central part and the lateral central part thereof, while memory arrays M are disposed in four regions divided by the cross areas A to E. As the peripheral circuits are disposed in the central parts of the chip or in each of the areas according to this constitution, the maximum transmission path of signals can be shortened to the half of a chip size substantially, and therefore DRAM designed to have a large storage capacity can be made to operate at a high speed.

4. 发明专利

JPS62275386A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPS62275386A
公开(公告)日：1987-11-30
申请号：JP11737486
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IWAI HIDETOSHI , MIYAZAWA KAZUYUKI , SAKUTA TOSHIYUKI , KIMURA KATSUTAKA , SHIMOHIGASHI KATSUHIRO , ETO JUN , TANAKA HITOSHI
IPC分类号： G11C11/401 , G11C11/34 , G11C29/00 , G11C29/14
摘要： PURPOSE:To easily recognize the occurrence of errors in a test mode by receiving signals read out of a memory arrays every plural bits to detect the coincidence or disagreement of these signals and transmitting the output signal having a medium level between the output high and low levels to an external output terminal by the dissident output. CONSTITUTION:A test circuit contained in a data input circuit DIB sets all multiplexers MPX in the selection states while the test circuit is active and then transmits write signals supplied from an external terminal Din to common complementary data lines CD0-CD3. Thus the same signals are written simultaneously in the unit of four apparent bits into four memory cells set in the selection states in a memory array M-ARY. In other words, the test circuit produces the output signal of a high or low level by an output circuit if the 4-bit read signals are coincident with each other at a high or low level. Then an output terminal Dout is set at an intermediate level if the 4-bit read signal is disagreement even with a single bit.

5. 发明专利

JPH06230043A VOLTAGE DETECTING CIRCUIT 失效
公开(公告)号：JPH06230043A
公开(公告)日：1994-08-19
申请号：JP1530693
申请日：1993-02-02
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ETO JUN , TANAKA HITOSHI , NAKAGOME YOSHINOBU , UEDA SHIGEKI , YAMAZAKI EIJI , AOKI MASAKAZU
IPC分类号： G01R19/165 , G01R19/32 , G11C11/407 , G11C11/409 , G11C29/00 , G11C29/02 , H01L21/822 , H01L27/04
摘要： PURPOSE:To detect decided voltage without being influenced by temperature and power supply voltage by comparing the quantities of a first current and a second current with each other, providing a current comparison means to output the compared result, and conforming the polarity of these current to each other. CONSTITUTION:The reference current flowing in M8 is compared with the current flowing in M6 in response to the voltage to be detected in a current comparison circuit ICI. When the current flowing in M6 becomes larger than the current flowing in M8 of the circuit ICI, a terminal 103 becomes high potential, and hence the output terminal 104 of an invertor INV becomes low potential. Meanwhile, in the reverse case, the terminal 104 becomes high potential. A charge pump circuit is controlled by the output signal of the INV, and stable internal boost voltage Vch is made without dependency of source voltage Vcc. Further, because the polarity of temperature dependency is sams as to the reference current for comparison and the current to be detected, temperature dependency of the voltage to be detected is eliminated. Thus, voltage detection without temperature dependency of the detected voltage of the voltage Vch and dependency of the voltage Vcc can be performed.

6. 发明专利

JPH05206752A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH05206752A
公开(公告)日：1993-08-13
申请号：JP1475192
申请日：1992-01-30
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TANAKA HITOSHI , NAKAGOME YOSHINOBU , ETO JUN , KAWAMOTO KOJI , SAKUTA TOSHIYUKI , IWAI HIDETOSHI , AOKI MASAKAZU
IPC分类号： H03F3/343
摘要： PURPOSE:To improve the stability and power consumption by generating a reference 1st constant current, generating a 2nd constant current proportional to the constant current by a current mirror circuit, supplying the current to a resistor and using a voltage across the resistor as a reference voltage. CONSTITUTION:A gate size of transistors(TRs) Q1, Q2 among P and N channel TRs Q1, 2 and Q3, 4 is equal to each other and a threshold voltage of the TR Q2 is set lower by DELTAVT. Moreover, the gate size and the threshold voltage of the TRs Q3, Q4 are equal to each other and form a current mirror circuit, then a constant current DELTAVT/RR flows to them. On the other hand, TRs Q5, Q6 form a current mirror circuit with the TRs Q1, Q4 and a current proportional to a current flowing to the TRs Q1, Q4 flows to the TRs Q5, Q6 and voltages VLN, VLA are stable reference voltages. Thus, number of differential amplifiers employed for a reference voltage generating circuit is reduced, the stability is improved and the power consumption is reduced.

7. 发明专利

JPH0528759A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0528759A
公开(公告)日：1993-02-05
申请号：JP18610091
申请日：1991-07-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ETO JUN , AOKI MASAKAZU , HORIGUCHI SHINJI , UEDA SHIGEKI , TANAKA HITOSHI , KAJITANI KAZUHIKO , TAKAHASHI TSUGIO , KAWAMOTO HIROSHI
IPC分类号： G11C11/407 , G05F1/46 , G11C5/14 , G11C11/401 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/04 , H01L27/10 , H01L27/108 , H03G11/00
摘要： PURPOSE:To offer the method of increasing a durability again a surge voltage added to a Vcc pin, suppressing the large fluctuation of power supply currents, and suppressing a noise generated by the fluctuation of the power supply currents, in a semiconductor integrated circuit using a voltage reducing circuit. CONSTITUTION:A series circuit 110 constituted of a capacitance and a resistor is arranged between a Vcc wiring 105 and a Vss wiring 106 in a semiconductor integrated circuit chip 100. The transmission of the surge voltage added to the Vcc pin to an inside circuit is delayed by the capacitance arranged between the Vcc wiring and the Vss wiring. And also, the area of an PN joint to the Vcc wiring is enlarged in order to increase current amounts to be allowed to flow. Thus, the durability against the surge voltage added to the Vcc pin can be increased. And also, a resonance frequency due to the inductance of a power source wiring at the outside of the semiconductor chip, and the capacitance of the power source wiring in the semiconductor chip can be decreased by the pertinent capacitance. Thus, the large change of the power supply currents can be reduced.

8. 发明专利

JPH04181589A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH04181589A
公开(公告)日：1992-06-29
申请号：JP30873990
申请日：1990-11-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： HORIGUCHI SHINJI , ETO JUN , AOKI MASAKAZU , NAKAGOME YOSHINOBU , TANAKA HITOSHI , ITO KIYOO
IPC分类号： G11C11/413 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/04 , H01L21/82 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enable DC failure to be recovered and an unneeded power consumption to be reduced by stopping supply of a power supply and a signal to each normal faulty memory block with a switch circuit and by using a preliminary block instead. CONSTITUTION:When there is a CD failure in a normal memory mat 10, power supplies VPL and VMP are supplied to a preliminary memory mat 20 only when an address between mats of the mat 10 are written into a ROM 35. Even if the memory is in operation state and the mat 10 is selected, a switch circuit 15 if OFF and no timing signal is supplied. On the other hand, the address signal between mats and an output of the ROM are compared by a comparison circuit 36 and the mat 10 is selected, thus enabling a switch circuit 25 of a mat 20 to be turned On and a timing signal to be supplied to the mat 20. Namely, supply of power supply and signal to the mat 10 is stopped by the circuit 15 and is supplied to the mat 20 instead.

9. 发明专利

JPH01241094A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01241094A
公开(公告)日：1989-09-26
申请号：JP6745388
申请日：1988-03-23
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI VLSI ENG
发明人： AKIBA TAKESADA , ETO JUN , TANAKA HITOSHI , HORIGUCHI SHINJI , NAKAGOME YOSHINOBU , AOKI MASAKAZU , ITO KIYOO
IPC分类号： G11C11/401 , G11C11/34 , G11C11/409 , G11C11/41 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To reduce the increase in chip dimension and delay in memory operation of the tile device so as to constitute the device in a highly integrated state by dividing data output amplifier groups provided at every divided sub-input/output line into two sets and arranging them on both sides of a memory array closely to the memory array as if the memory array is put between the amplifier groups. CONSTITUTION:A very small potential difference is produced in a data line depending upon the information accumulated in memory cells MC. After the potential difference is amplified by means of a sense amplifier, the output line of a decoder YD becomes high in level and the information of the data line is read out to a data output amplifier AMP through a sub-input/output line. When, for example, the Y-decoder output line in the lower section of a sub-array is selected by the decoder YD, the information of the data line is read out to the data output amplifier AMP in the lower section of this chip through a sub-input/output line IPb. Since the data output amplifiers are arranged above and beneath the memory array in such way, lengths of the wirings connecting the sub-input/output lines with the data output amplifiers become shorter. Therefore, the parasitic capacities and resistances can be reduced and the operating speed of this memory can be improved.

10. 发明专利

JPH09102592A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH09102592A
公开(公告)日：1997-04-15
申请号：JP8991196
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KAJITANI KAZUHIKO , YAMAGUCHI YASUNORI , OSHIMA KAZUYOSHI , YAMAZAKI TAKASHI , MIYAMOTO EIJI , SAKAI YUJI , SAWADA JIRO , ETO JUN , HORIGUCHI SHINJI , IKENAGA SHINICHI , KUMADA ATSUSHI , TSUNOSAKI MANABU , KASAMA YASUHIRO , UDO SHINJI , YOSHIOKA HIROSHI , SAITO HIROMI , TAKANO MITSUHIRO , MORINO MAKOTO , MIYATAKE SHINICHI , MATSUMOTO TETSUO
IPC分类号： G11C11/401 , H01L21/82 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To increase the memory capacity or large scale integration by providing a step buffer area made of a dummy conductor layer between a memory array and a peripheral circuit by sing a plurality of dynamic memory cells having a laminated capacitor as a memory cell formed in the memory array. SOLUTION: A memory chip has memory arrays M divided into four by cross areas made of areas A to E. The arrays M divided into the four are disposed by extending a word line in the lateral direction, and disposed by extending a data line (bit line or digit line) in a vertical direction. A step buffer area made of a dummy wiring layer is provided between the arrays M and the peripheral circuit. A guard ring is disposed under the step buffer area to stabilize the characteristics.

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