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1. 发明专利

JPH01241094A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01241094A
公开(公告)日：1989-09-26
申请号：JP6745388
申请日：1988-03-23
申请人： HITACHI LTD , HITACHI DEVICE ENG , HITACHI VLSI ENG
发明人： AKIBA TAKESADA , ETO JUN , TANAKA HITOSHI , HORIGUCHI SHINJI , NAKAGOME YOSHINOBU , AOKI MASAKAZU , ITO KIYOO
IPC分类号： G11C11/401 , G11C11/34 , G11C11/409 , G11C11/41 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To reduce the increase in chip dimension and delay in memory operation of the tile device so as to constitute the device in a highly integrated state by dividing data output amplifier groups provided at every divided sub-input/output line into two sets and arranging them on both sides of a memory array closely to the memory array as if the memory array is put between the amplifier groups. CONSTITUTION:A very small potential difference is produced in a data line depending upon the information accumulated in memory cells MC. After the potential difference is amplified by means of a sense amplifier, the output line of a decoder YD becomes high in level and the information of the data line is read out to a data output amplifier AMP through a sub-input/output line. When, for example, the Y-decoder output line in the lower section of a sub-array is selected by the decoder YD, the information of the data line is read out to the data output amplifier AMP in the lower section of this chip through a sub-input/output line IPb. Since the data output amplifiers are arranged above and beneath the memory array in such way, lengths of the wirings connecting the sub-input/output lines with the data output amplifiers become shorter. Therefore, the parasitic capacities and resistances can be reduced and the operating speed of this memory can be improved.

2. 发明专利

JP2003132679A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003132679A
公开(公告)日：2003-05-09
申请号：JP2001324458
申请日：2001-10-23
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： AKIBA TAKESADA , HORIGUCHI SHINJI
IPC分类号： G11C11/407 , G11C11/409 , H01L21/822 , H01L27/04 , H02M3/07
摘要： PROBLEM TO BE SOLVED: To realize an internal boosting circuit in which output voltage of external positive power source voltage is constant and is operated stably in a wide voltage range from low voltage to high voltage, also reliability of elements is secured, and a semiconductor chip. SOLUTION: One voltage drop circuit 12 and two boosting circuits 13, 14 are provided in a chip, the voltage drop circuit 12 generates constant voltage VARY from external voltage VDD and supplies voltage to a bit line, the first boosting circuit 13 supplies external voltage VDD, generates internal boosting voltage VPPL, and supplies voltage to a pre-charge circuit of a bit line, the second boosting circuit 14 supplies internal boosting voltage VPPL, generates internal boosting voltage VPPH, and supplies voltage to a word line. Voltage difference between VPPL and VARY is assumed to constant, and adjusted higher than a threshold value of MOS constituting the pre-charge circuit, and voltage difference between VPPH and VARY is assumed to constant, and adjusted higher than a threshold value of MOS constituting a memory cell.

3. 发明专利

JP2002197865A DATA PROCESSING SYSTEM 审中-公开
公开(公告)号：JP2002197865A
公开(公告)日：2002-07-12
申请号：JP2001321321
申请日：2001-10-19
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KAWAHARA TAKAYUKI , KAWAJIRI YOSHIKI , AKIBA TAKESADA , HORIGUCHI SHINJI , WATABE TAKAO , KITSUKAWA GORO , KAWASE YASUSHI , TACHIBANA RIICHI , AOKI MASAKAZU
IPC分类号： G11C11/413 , G11C11/401 , G11C11/407 , G11C11/418 , G11C16/06 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To reduce current consumption at the time of standby in a semiconductor integrated circuit M using a plurality of CMOS circuits Ci using minute MOS transistors. SOLUTION: This system is switched to a standby state by signals (/RAS signal, /CAS signal) controlling a semiconductor integrated circuit M. A sub- threshold current flowing in a CMOS circuit of the semiconductor circuit is reduced by providing a power source switch to be turned off at the time of standby.

4. 发明专利

JPH05135580A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH05135580A
公开(公告)日：1993-06-01
申请号：JP29547791
申请日：1991-11-12
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KAWAHARA TAKAYUKI , KAWAJIRI YOSHIKI , AKIBA TAKESADA , HORIGUCHI SHINJI , KITSUKAWA GORO , AOKI MASAKAZU
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/4096
摘要： PURPOSE:To provide a semiconductor storage device of the small current consumption by using a current supplied once from a power supply to another circuit without sending immediately the current to ground. CONSTITUTION:The switches SP and SN are provided between the 1st common source lines PP1, PN1 and the 2nd common source lines PP2, PN2 to cause the short circuits among these source lines. The potentials of the 2nd common source lines are changed with the electric charge of the 1st common source lines opened up to the VD-VS amplitude. The data lines connected to the 2nd common source lines are amplified up to the half of the original amplitude and then amplified by a sense amplifier. As a result, the charging/discharging currents of the data lines can be virtually halved.

5. 发明专利

JPH0547179A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0547179A
公开(公告)日：1993-02-26
申请号：JP1172792
申请日：1992-01-27
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KAWAHARA TAKAYUKI , SAKATA TAKESHI , ITO KIYOO , AKIBA TAKESADA , KITSUKAWA GORO , KAWAJIRI YOSHIKI
IPC分类号： G11C11/409 , G11C7/06 , G11C11/401 , G11C11/4091 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To provide a semiconductor device with high precision and high speed by changing the precharging voltage of an input line and cancelling the dispersion of the characteristic of individual amplifier circuit. CONSTITUTION:First of all, switch group S11, S12, S21 and S22 are turned off, the sources of a first and a second MOS transistors Ml and M2 are made the same potential by a means DS, signal lines 11, 12 are precharged to the voltage of the threshold voltage of the M1, M2 or above. Then, by turning on/off the S11, S12, the difference of the threshold voltages of the M1, M2 is cancelled with the flow of a prescribed current. When a signal generating means MC is operated at this condition, a current difference corresponding to a signal difference flows to the M1, M2 and is outputted from terminals O1, O2. Thus, high speed amplifying operation independent of the characteristic fluctuation of an element is performed.

6. 发明专利

JPH04318394A SEMICONDUCTOR DRIVING CIRCUIT 失效
公开(公告)号：JPH04318394A
公开(公告)日：1992-11-09
申请号：JP8654991
申请日：1991-04-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KAWAJIRI YOSHIKI , KITSUKAWA GORO , KAWAHARA TAKAYUKI , AKIBA TAKESADA , ITO KIYOO
IPC分类号： G11C11/409 , G11C11/407 , H01L21/8238 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H03K19/0175
摘要： PURPOSE:To speed up and simultaneously to prevent the slow down of the operations during a low voltage operation by controlling the gate of a load driving MOS transistor through the use of the in-circuit signal which has a higher amplitude than the output amplitude. CONSTITUTION:First, power supplies VSS and VCC of an inverter circuit consisting of MP4 and MN4, which drive a load capacitor CL, separate from power supplies VSL and VCH of the circuit which drives the inverter circuit and make the voltage value VSL be lower than VSS and make VCH be higher than VCC. As a result, the gate voltage of the MOS transistor, which drives the load capacitor CL, becomes large, eliminate the effect of the threshold voltage of p MOS MP4 and a high speed operation is realized. Furthermore, when power supply voltage becomes lower than 1.5 volts, a stable operation is realized without lowering the threshold voltage.

7. 发明专利

JPH03214811A SEMICONDUCTOR CIRCUIT 失效
公开(公告)号：JPH03214811A
公开(公告)日：1991-09-20
申请号：JP812290
申请日：1990-01-19
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KATO SHISEI , KITSUKAWA GORO , AKIBA TAKESADA , KAWAJIRI YOSHIKI , ITO KIYOO , KAWAHARA TAKAYUKI , KAWASE YASUSHI
IPC分类号： G11C11/414 , H03K17/04
摘要： PURPOSE:To make the operating speed at each point on an output line equal to each other by arranging plural current sources of an emitter follower circuit to different positions in a scattered mode on the emitter follower output line. CONSTITUTION:Current sources IE1-IE3 discharging an emitter follower circuit are arranged in the scattered mode on an output line. Since the discharge at output points S1, S2, S3 is implemented in terms of addition of a current source IE0 at an emitter follower output point and current sources IE1-IE3 in the vicinity of each output point, the operating speed on each output line is identical to each other independently of the wiring resistor and the wiring capacitance. Through the constitution above, the circuit speed is made high without increasing the current consumption and the operating timing of a post-stage circuit is easily synchronized.

8. 发明专利

JPH02189795A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH02189795A
公开(公告)日：1990-07-25
申请号：JP761889
申请日：1989-01-18
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KAWAHARA TAKAYUKI , ITO KIYOO , KITSUKAWA GORO , KAWAJIRI YOSHIKI , WATABE TAKAO , HIGUCHI HISAYUKI , AKIBA TAKESADA , KATO SHISEI
IPC分类号： G11C11/417 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/414 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To obtain a semiconductor memory device with fast operation and low noise by providing a level conversion circuit used as decorder in common connecting a circuit part with a small amplitude and a circuit part with a large amplitude and operating circuit parts other than a circuit directly controlling a MOS memory cell array with a small signal amplitude. CONSTITUTION:Peripheral circuits other than a circuit controlling directly a MOS memory cell C requiring a signal with a large amplitude (part excluding predecoder in decoder driver circuits 8X, 8Y) have a small signal level. That is, the amplitude of an internal operation signal and an output signal for a control circuit 9 and an address buffer 5X, an internal operation signal and an input output signal for a predecoder 20 is selected small amplitude Va and the signal with the amplitude Va is level-converted by a decoder word driver 21 (decoder and level conversion circuit and driver) to drive a MOS memory cell C at a large amplitude Vb. The Y system (data line system) circuits 5Y, 8Y are operated similarly as the X system circuits 5X, 8X. Thus, a semiconductor device with high speed and low noise is obtained.

9. 发明专利

JP2003068079A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2003068079A
公开(公告)日：2003-03-07
申请号：JP2001261123
申请日：2001-08-30
申请人： Hitachi Device Eng Co Ltd , Hitachi Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立製作所
发明人： AKIBA TAKESADA , UEDA SHIGEKI , TACHIBANA RIICHI , HORIGUCHI SHINJI
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/409 , G11C29/08 , G11C29/00
CPC分类号： G11C5/147 , G11C11/4074 , G11C2207/2227
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a current consumption during non-operation is reduced in a system in which a plurality of chips having commonly a power source, an address signal, and a data bus are mounted. SOLUTION: This circuit is provided with an internal circuit comprising a memory array which can supply and stop operation voltage selectively through a switch means, when supply and stop of operation voltage by the switch means are controlled by an input circuit receiving the prescribed control signal and memory operation is not performed, super power consumption can be realized by reducing a DC current and a leak current.
摘要翻译：要解决的问题：提供一种其中安装有共同具有电源，地址信号和数据总线的多个芯片的系统中减少了非操作期间的电流消耗的半导体存储器。解决方案：该电路具有内部电路，该内部电路包括存储器阵列，该存储器阵列可以通过开关装置选择性地提供和停止工作电压，当开关装置的工作电压的供应和停止由接收规定的控制信号的输入电路控制时，不执行存储器操作，可以通过减少DC电流和泄漏电流来实现超级功耗。

10. 发明专利

JP2000076854A Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：JP2000076854A
公开(公告)日：2000-03-14
申请号：JP16931299
申请日：1999-06-16
申请人： Hitachi Device Eng Co Ltd , Hitachi Ltd , 日立デバイスエンジニアリング株式会社 , 株式会社日立製作所
发明人： KAWAHARA TAKAYUKI , KAWAJIRI YOSHIKI , AKIBA TAKESADA , HORIGUCHI SHINJI , WATABE TAKAO , KITSUKAWA GORO , KAWASE YASUSHI , TACHIBANA RIICHI , AOKI MASAKAZU
IPC分类号： G06F1/32 , G11C11/407 , G11C11/413 , G11C27/02 , H01L21/8242 , H01L27/108 , H03K19/00 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To reduce a consumption current at a standby time in a semiconductor integrated circuit using a plurality of CMOS circuits using a small MOS transistor. SOLUTION: The device parameter of a switching transistor S1 is set to that the leakage current of the S1 for composing a power supply switch that is turned off at a standby time becomes smaller than the total of the sub threshold current of a p-channel of n-channel MOS in an off state of a plurality of CMOS circuits Ci. As a result, the current of a plurality of CMOS circuits C1 at a standby time becomes a small leakage current of the switching transistor S1, and not a large sub threshold current of the Ci using a small MOS.
摘要翻译：要解决的问题：使用使用小型MOS晶体管的多个CMOS电路在半导体集成电路中在待机时减少消耗电流。解决方案：将开关晶体管S1的器件参数设定为在待机时断开的用于构成电源开关的S1的漏电流变得小于p沟道的次级阈值电流的总和处于多个CMOS电路Ci的截止状态的n沟道MOS。结果，待机时的多个CMOS电路C1的电流成为开关晶体管S1的小的漏电流，而不是使用小的MOS的Ci的大的次阈值电流。

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