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1. 发明申请

US20110238870A1 Memory System With Command Filtering 审中-公开
标题翻译：带有命令过滤的内存系统
公开(公告)号：US20110238870A1
公开(公告)日：2011-09-29
申请号：US13131557
申请日：2009-11-17
申请人： Frederick A. Ware , Wayne Richardson , Kishore Kasamsetty
发明人： Frederick A. Ware , Wayne Richardson , Kishore Kasamsetty
IPC分类号： G06F13/28
CPC分类号： G11C29/56 , G01R31/3171 , G11C29/028 , G11C29/48 , G11C29/50012 , G11C29/56012
摘要： A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.
摘要翻译：存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控制器。链路的定时和电压裕度被定期校准，以减少位误差。高速请求链接使校准变得复杂，因为通过未校准的请求链接发出的命令可能被存储器件错误地解释。错误解释的命令可能会中断校准过程（例如，写命令可能被误解为掉电命令）。存储器控制器使用单独的低速控制接口来解决这个问题，发出一个过滤器命令，指示当处于校准模式时存储器件可能会破坏潜在的破坏性请求。

2. 发明申请

US20110055451A1 CROSS-THREADED MEMORY SYSTEM 有权
标题翻译：十字路口存储系统
公开(公告)号：US20110055451A1
公开(公告)日：2011-03-03
申请号：US12828526
申请日：2010-07-01
申请人： Frederick A. Ware , Kishore Kasamsetty
发明人： Frederick A. Ware , Kishore Kasamsetty
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
摘要： In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
摘要翻译：在数据处理系统中，缓冲器集成电路（IC）装置包括多个控制接口，多个存储器接口和切换电路，以根据路径选择值将每个控制接口同时耦合到相应的一个存储器接口。多个请求者IC设备分别耦合到控制接口，并且多个存储器IC设备分别耦合到存储器接口。

3. 发明申请

US20080028127A1 CROSS-THREADED MEMORY SYSTEM 有权
标题翻译：十字路口存储系统
公开(公告)号：US20080028127A1
公开(公告)日：2008-01-31
申请号：US11460582
申请日：2006-07-27
申请人： Frederick A. Ware , Kishore Kasamsetty
发明人： Frederick A. Ware , Kishore Kasamsetty
IPC分类号： G06F12/00
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
摘要： In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
摘要翻译：在数据处理系统中，缓冲器集成电路（IC）装置包括多个控制接口，多个存储器接口和切换电路，以根据路径选择值将每个控制接口同时耦合到相应的一个存储器接口。多个请求者IC设备分别耦合到控制接口，并且多个存储器IC设备分别耦合到存储器接口。

4. 发明授权

US08510495B2 Cross-threaded memory system 有权
标题翻译：跨线程内存系统
公开(公告)号：US08510495B2
公开(公告)日：2013-08-13
申请号：US12828526
申请日：2010-07-01
申请人： Frederick A. Ware , Kishore Kasamsetty
发明人： Frederick A. Ware , Kishore Kasamsetty
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
摘要： In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
摘要翻译：在数据处理系统中，缓冲器集成电路（IC）装置包括多个控制接口，多个存储器接口和切换电路，以根据路径选择值将每个控制接口同时耦合到相应的一个存储器接口。多个请求者IC设备分别耦合到控制接口，并且多个存储器IC设备分别耦合到存储器接口。

5. 发明授权

US07769942B2 Cross-threaded memory system 有权
标题翻译：跨线程内存系统
公开(公告)号：US07769942B2
公开(公告)日：2010-08-03
申请号：US11460582
申请日：2006-07-27
申请人： Frederick A. Ware , Kishore Kasamsetty
发明人： Frederick A. Ware , Kishore Kasamsetty
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F3/061 , G06F3/0647 , G06F3/0683 , G06F12/00 , G06F12/02 , G06F13/1657 , G06F13/1668 , G06F13/4282 , G11C5/02
摘要： In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requester IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.
摘要翻译：在数据处理系统中，缓冲器集成电路（IC）装置包括多个控制接口，多个存储器接口和切换电路，以根据路径选择值将每个控制接口同时耦合到相应的一个存储器接口。多个请求者IC设备分别耦合到控制接口，并且多个存储器IC设备分别耦合到存储器接口。

6. 发明授权

US09330735B2 Memory with deferred fractional row activation 有权
$Memory with deferred fractional row activation$
标题翻译：具有延迟分数行激活的内存
公开(公告)号：US09330735B2
公开(公告)日：2016-05-03
申请号：US13640084
申请日：2012-06-08
申请人： James Edward Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
发明人： James Edward Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC分类号： G11C7/00 , G11C7/06 , G11C5/02 , G11C7/10 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/08
CPC分类号： G11C7/1039 , G11C5/025 , G11C7/06 , G11C7/065 , G11C7/08 , G11C7/12 , G11C7/222 , G11C8/08 , G11C8/10 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the sub-row to be activated.
摘要翻译：存储器组件内的行激活操作相对于子行执行，而不是完整的存储行，以减少功耗。此外，除了响应于行命令激活子代以外，子代激活操作被延迟，直到接收到指定要执行的列操作的列命令和要被激活的子行。

7. 发明授权

US09287239B2 Techniques for interconnecting stacked dies using connection sites 有权
标题翻译：使用连接点互连堆叠管芯的技术
公开(公告)号：US09287239B2
公开(公告)日：2016-03-15
申请号：US13641680
申请日：2011-04-13
申请人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
发明人： Frederick A. Ware , Ely Tsern , Thomas Vogelsang
IPC分类号： H01L25/16 , H01L23/538 , H01L25/065 , H01L25/18 , H01L23/48
CPC分类号： H01L23/481 , G06F3/0604 , G06F3/0629 , G06F3/0673 , G06F2213/0038 , H01L25/0657 , H01L25/18 , H01L2224/131 , H01L2224/16146 , H01L2225/06544 , H01L2924/014
摘要： An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
摘要翻译：集成电路管芯包括至少位于其连续区域内的集成电路管芯的表面上的导电连接位置。集成电路还包括位于连续区域外的核心电路。核心电路耦合到至少一个连接位置。

8. 发明授权

US08918669B2 Mesochronous signaling system with clock-stopped low power mode 有权
标题翻译：具有时钟停止低功耗模式的中间信号系统
公开(公告)号：US08918669B2
公开(公告)日：2014-12-23
申请号：US13132094
申请日：2009-07-09
申请人： Frederick A. Ware , Robert E. Palmer , John W. Poulton , Andrew M. Fuller
发明人： Frederick A. Ware , Robert E. Palmer , John W. Poulton , Andrew M. Fuller
IPC分类号： G06F1/04 , G06F1/08 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C7/04 , G11C11/4096 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译：在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。

9. 发明申请

US20140159961A1 LOW-COST TRACKING SYSTEM 有权
标题翻译：低成本跟踪系统
公开(公告)号：US20140159961A1
公开(公告)日：2014-06-12
申请号：US14234623
申请日：2012-08-03
申请人： Frederick A. Ware , Farshid Aryanfar , John Brooks
发明人： Frederick A. Ware , Farshid Aryanfar , John Brooks
IPC分类号： G01S5/02
CPC分类号： G01S13/84 , A63F13/216 , G01S5/0294 , G01S5/06 , G01S7/52004 , G01S13/878 , G01S2007/4091
摘要： A method of tracking a second electronic device with respect to a first electronic device is disclosed. The method includes transmitting a first waveform of a first frequency along a first fixed path associated with the first device. A second waveform having a frequency based on the first frequency is wirelessly transmitted from the first device to the second device along a first wireless path. The second waveform is wirelessly transmitted from the second device to the first device along a second wireless path. The first and second waveforms are received at the phase comparator circuit. A first phase relationship of the received first waveform is then compared to a second phase relationship of the received re-transmitted waveform. A coordinate of the second device is determined with respect to a reference coordinate based on the comparing.
摘要翻译：公开了一种相对于第一电子设备跟踪第二电子设备的方法。该方法包括沿着与第一设备相关联的第一固定路径发送第一频率的第一波形。具有基于第一频率的频率的第二波形沿着第一无线路径从第一设备无线地发送到第二设备。第二波形沿着第二无线路径从第二设备无线发送到第一设备。第一和第二波形在相位比较器电路处被接收。然后将接收的第一波形的第一相位关系与所接收的重发波形的第二相位关系进行比较。基于比较，相对于参考坐标确定第二装置的坐标。

10. 发明申请

US20140003131A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20140003131A1
公开(公告)日：2014-01-02
申请号：US13860825
申请日：2013-04-11
申请人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
发明人： Frederick A. Ware , Lawrence Lai , Chad A. Bellows , Wayne S. Richardson
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

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