专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110238870A1 Memory System With Command Filtering 审中-公开
标题翻译：带有命令过滤的内存系统
公开(公告)号：US20110238870A1
公开(公告)日：2011-09-29
申请号：US13131557
申请日：2009-11-17
申请人： Frederick A. Ware , Wayne Richardson , Kishore Kasamsetty
发明人： Frederick A. Ware , Wayne Richardson , Kishore Kasamsetty
IPC分类号： G06F13/28
CPC分类号： G11C29/56 , G01R31/3171 , G11C29/028 , G11C29/48 , G11C29/50012 , G11C29/56012
摘要： A memory system includes a memory controller coupled to at least one memory device via high-speed data and request links. The timing and voltage margins of the links are periodically calibrated to reduce bit error. The high-speed request links complicate calibration because commands issued over the uncalibrated request links can be erroneously interpreted by the memory device. Misinterpreted commands can disrupt the calibration procedure (e.g., a write command might be misinterpreted as a power-down command). The memory controller addresses this problem using a separate, low-speed control interface to issue a filter command that instructs the memory device to decline potentially disruptive requests when in a calibration mode.
摘要翻译：存储器系统包括经由高速数据和请求链路耦合到至少一个存储器设备的存储器控制器。链路的定时和电压裕度被定期校准，以减少位误差。高速请求链接使校准变得复杂，因为通过未校准的请求链接发出的命令可能被存储器件错误地解释。错误解释的命令可能会中断校准过程（例如，写命令可能被误解为掉电命令）。存储器控制器使用单独的低速控制接口来解决这个问题，发出一个过滤器命令，指示当处于校准模式时存储器件可能会破坏潜在的破坏性请求。

2. 发明申请

US20110211415A1 Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control 有权
标题翻译：集成电路存储器件，具有交错行和列控制的系统和方法
公开(公告)号：US20110211415A1
公开(公告)日：2011-09-01
申请号：US13103548
申请日：2011-05-09
申请人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
发明人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C7/1018 , G11C7/1039 , G11C7/1048
摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.
摘要翻译：集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

3. 发明授权

US08391099B2 Integrated circuit memory device, system and method having interleaved row and column control 有权
标题翻译：集成电路存储器件，具有交错列和列控制的系统和方法
公开(公告)号：US08391099B2
公开(公告)日：2013-03-05
申请号：US13103548
申请日：2011-05-09
申请人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
发明人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
IPC分类号： G11C8/18
CPC分类号： G11C7/1018 , G11C7/1039 , G11C7/1048
摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.
摘要翻译：集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

4. 发明授权

US07940598B2 Integrated circuit memory device, system and method having interleaved row and column control 有权
标题翻译：集成电路存储器件，具有交错列和列控制的系统和方法
公开(公告)号：US07940598B2
公开(公告)日：2011-05-10
申请号：US12177357
申请日：2008-07-22
申请人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
发明人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C7/1018 , G11C7/1039 , G11C7/1048
摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.
摘要翻译：集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

5. 发明申请

US20080279032A1 Integrated Circuit Memory Device, System And Method Having Interleaved Row And Column Control 有权
标题翻译：集成电路存储器件，具有交错行和列控制的系统和方法
公开(公告)号：US20080279032A1
公开(公告)日：2008-11-13
申请号：US12177357
申请日：2008-07-22
申请人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
发明人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
IPC分类号： G11C8/10
CPC分类号： G11C7/1018 , G11C7/1039 , G11C7/1048
摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.
摘要翻译：集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

6. 发明授权

US07420874B2 Integrated circuit memory device, system and method having interleaved row and column control 有权
标题翻译：集成电路存储器件，具有交错列和列控制的系统和方法
公开(公告)号：US07420874B2
公开(公告)日：2008-09-02
申请号：US11099947
申请日：2005-04-06
申请人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
发明人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
IPC分类号： G11C8/18
CPC分类号： G11C7/1018 , G11C7/1039 , G11C7/1048
摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device includes an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.
摘要翻译：集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号组。行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

7. 发明申请

US20060227646A1 Integrated circuit memory device, system and method having interleaved row and column control 有权
标题翻译：集成电路存储器件，具有交错列和列控制的系统和方法
公开(公告)号：US20060227646A1
公开(公告)日：2006-10-12
申请号：US11099947
申请日：2005-04-06
申请人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
发明人： Kishore Kasamsetty , Lawrence Lai , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C7/1018 , G11C7/1039 , G11C7/1048
摘要： An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second clock frequency, output independent column and row control internal signals to a memory core in response to memory commands in the request packets. An integrated circuit memory device comprises an interface having separate row and column decode logic circuits for providing independent sets of row and control signals. A row decode logic circuit includes a first row decode logic circuit that provides a first row control signal, such as a row address, and a second row decode logic circuit that provides a second row control signal. A column decode logic circuit includes a first column decode logic circuit that provides a first column control signal, such as a column address and a second column logic circuit that provides a second column control signal.
摘要翻译：集成电路存储器件，系统和方法实施例以第一时钟频率解码在互连上传送的交错的行和列请求分组。独立的行解码逻辑和列解码逻辑以相对较慢的第二时钟频率计时，响应于请求数据包中的存储器命令，将独立的列和行控制内部信号输出到存储器内核。集成电路存储器件包括具有单独的行和列解码逻辑电路的接口，用于提供独立的行和控制信号集合。行解码逻辑电路包括提供诸如行地址的第一行控制信号的第一行解码逻辑电路和提供第二行控制信号的第二行解码逻辑电路。列解码逻辑电路包括提供诸如列地址的第一列控制信号的第一列解码逻辑电路和提供第二列控制信号的第二列逻辑电路。

8. 发明申请

US20080062807A1 MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括集成电路存储器件的多字段寻址模式存储器系统
公开(公告)号：US20080062807A1
公开(公告)日：2008-03-13
申请号：US11853708
申请日：2007-09-11
申请人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
发明人： Frederick Ware , Lawrence Lai , Chad Bellows , Wayne Richardson
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12 , G11C8/16
摘要： A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
摘要翻译：存储器系统包括主设备，诸如图形控制器或处理器，以及以双列寻址模式可操作的集成电路存储器件。集成电路存储器件包括一个接口和列解码器，以访问一行存储单元或存储体中的一页。在第一操作模式期间，响应于第一列地址可访问第一存储体中的第一行存储单元。在第二操作模式期间，响应于列周期时间间隔期间的第二列地址，可访问第一行存储单元中的第一多个存储单元。响应于列周期时间间隔期间的第三列地址，可访问第一行存储单元中的第二多个存储单元。第一和第二多个存储单元可以从该接口同时访问。

9. 发明申请

US20070268765A1 Integrated Circuit Memory Device Having Dynamic Memory Bank Count and Page Size 有权
标题翻译：具有动态存储器计数和页面大小的集成电路存储器件
公开(公告)号：US20070268765A1
公开(公告)日：2007-11-22
申请号：US11834915
申请日：2007-08-07
申请人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
发明人： Steven Woo , Michael Ching , Chad Bellows , Wayne Richardson , Kurt Knorpp , Jun Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/106 , G11C7/065 , G11C7/1045 , G11C7/1051
摘要： An integrated circuit memory device has a storage array with an adjustable number of memory banks, a row of sense amplifiers to access storage cells in the storage array; and memory access control circuitry. The memory access control circuitry provides a first number of memory banks and a first page size in the integrated circuit memory device in a first mode of operation, and provides a second number of memory banks and a second page size in the integrated circuit memory device in a second mode of operation. The memory access control circuitry includes logic circuitry to adjust the number of memory banks in the integrated circuit memory device, and to adjust the page size of the integrated circuit memory device.
摘要翻译：集成电路存储器件具有可调节数量的存储体的存储阵列，一行读出放大器，用于存取存储阵列中的存储单元; 和存储器访问控制电路。存储器访问控制电路在第一操作模式下在集成电路存储器件中提供第一数量的存储体和第一页面大小，并且在集成电路存储器件中提供第二数量的存储体和第二页面尺寸第二种操作模式。存储器访问控制电路包括用于调整集成电路存储器件中的存储体的数量的逻辑电路，并且调整集成电路存储器件的页面大小。

10. 发明申请

US20050276261A1 Communication channel calibration using feedback 有权
标题翻译：通信通道校准使用反馈
公开(公告)号：US20050276261A1
公开(公告)日：2005-12-15
申请号：US10864897
申请日：2004-06-09
申请人： Jun Kim , Wayne Richardson , Glenn Chiu
发明人： Jun Kim , Wayne Richardson , Glenn Chiu
IPC分类号： H04L12/56
CPC分类号： H04B17/11 , H04L5/1438 , H04L25/03343 , H04L2025/03802
摘要： A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.
摘要翻译：用于校准耦合第一和第二组件的通信信道的方法包括在第二组件上传输数据信号从第一分量到通信信道上的第二分量，以及感测数据信号的相位等特征。关于感测到的特性的信息使用辅助信道反馈到第一分量。响应于该信息，在第一组件上调整用于发射机的可调参数，例如相位。而且，感测从第二组件上的发射机接收到的数据信号的特性，并用于调整第一组件上的接收机的可调参数。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式