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1. 发明申请

US20070152276A1 High performance CMOS circuits, and methods for fabricating the same 审中-公开
标题翻译：高性能CMOS电路及其制造方法
公开(公告)号：US20070152276A1
公开(公告)日：2007-07-05
申请号：US11323578
申请日：2005-12-30
申请人： John Arnold , Glenn Biery , Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Michael Gribelyuk , Young-Hee Kim , Barry Linder , Vijay Narayanan , Joseph Newbury , Vamsi Paruchuri , Michelle Steen
发明人： John Arnold , Glenn Biery , Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Michael Gribelyuk , Young-Hee Kim , Barry Linder , Vijay Narayanan , Joseph Newbury , Vamsi Paruchuri , Michelle Steen
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/823842
摘要： The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits that each contains at least a first and a second gate stacks. The first gate stack is located over a first device region (e.g., an n-FET device region) in a semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer, a metallic gate conductor, and a silicon-containing gate conductor. The second gate stack is located over a second device region (e.g., a p-FET device region) in the semiconductor substrate and comprises at least, from bottom to top, a gate dielectric layer and a silicon-containing gate conductor. The first and second gate stacks can be formed over the semiconductor substrate in an integrated manner by various methods of the present invention.
摘要翻译：本发明涉及互补金属氧化物半导体（CMOS）电路，其各自包含至少第一和第二栅极堆叠。第一栅极堆叠位于半导体衬底中的第一器件区域（例如，n-FET器件区域）上，并且至少从底部至顶部包括栅极介电层，金属栅极导体和含硅的门导体。第二栅极堆叠位于半导体衬底中的第二器件区域（例如，p-FET器件区域）上，并且至少包括从栅极电介质层和含硅栅极导体的底部到顶部。可以通过本发明的各种方法以集成的方式在半导体衬底上形成第一和第二栅极叠层。

2. 发明申请

US20060237796A1 Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices 有权
标题翻译：使用金属/金属氮化物双层作为自对准积极缩放的CMOS器件中的栅电极
公开(公告)号：US20060237796A1
公开(公告)日：2006-10-26
申请号：US11111592
申请日：2005-04-21
申请人： Eduard Cartier , Matthew Copel , Bruce Doris , Rajarao Jammy , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri , Keith Wong
发明人： Eduard Cartier , Matthew Copel , Bruce Doris , Rajarao Jammy , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri , Keith Wong
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a worfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
摘要翻译：本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。根据本发明，至少一个nMOS器件包括栅堆叠，其包括栅极电介质，功能小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。本发明还提供了制造这种CMOS结构的方法。

3. 发明申请

US20070148838A1 Metal gate CMOS with at least a single gate metal and dual gate dielectrics 有权
标题翻译：具有至少一个栅极金属和双栅极电介质的金属栅极CMOS
公开(公告)号：US20070148838A1
公开(公告)日：2007-06-28
申请号：US11320330
申请日：2005-12-28
申请人： Bruce Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri
发明人： Bruce Doris , Young-Hee Kim , Barry Linder , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/8234
CPC分类号： H01L21/823857 , H01L21/823878 , H01L21/84
摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.
摘要翻译：提供了包括位于半导体衬底的表面上的至少一个nFET和至少一个pFET的互补金属氧化物半导体（CMOS）结构。根据本发明，nFET和pFET都包括至少一个栅极金属，并且nFET栅极堆叠被设计成具有不具有净负电荷的栅极电介质堆叠，并且pFET栅极堆叠被工程化以具有栅极电介质堆没有净正电荷。特别地，本发明提供了一种CMOS结构，其中nFET栅极堆叠被设计成包括带边缘功函数，并且pFET栅极堆叠被设计为具有1/4间隙功函数。在本发明的一个实施例中，第一栅极电介质堆叠包括第一高k电介质和含碱土金属的层或含稀土金属的层，而第二高k栅介质叠层包括第二高k电介质。

4. 发明申请

US20070152273A1 High performance circuit with metal and polygate electrodes 有权
标题翻译：具有金属和多孔电极的高性能电路
公开(公告)号：US20070152273A1
公开(公告)日：2007-07-05
申请号：US11323564
申请日：2005-12-30
申请人： Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Young-Hee Kim , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen , Ying Zhang
发明人： Alessandro Callegari , Tze-Chiang Chen , Michael Chudzik , Bruce Doris , Young-Hee Kim , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen , Ying Zhang
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L21/823857 , H01L21/28044 , H01L21/28088 , H01L21/823842 , H01L29/4925 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： A semiconductor structure and a method of fabricating the same wherein the structure includes at least one nFET device and a least one pFET device, where at least one of the devices is a thinned Si-containing gated device and the other device is a metal gated device are provided. That is, a semiconductor structure is provided wherein at least one of the nFET or pFET devices includes a gate electrode stack comprising a thinned Si-containing electrode, i.e., polysilicon electrode, and an overlying first metal, while the other device includes a gate electrode stack that includes at least the first metal gate, without the thinned Si-containing electrode.
摘要翻译：一种半导体结构及其制造方法，其中该结构包括至少一个nFET器件和至少一个pFET器件，其中至少一个器件是薄化的含Si门控器件，另一个器件是金属门控器件被提供。也就是说，提供半导体结构，其中nFET或pFET器件中的至少一个包括包括稀薄的含Si电极，即多晶硅电极和上覆的第一金属的栅极电极堆叠，而另一个器件包括栅电极堆叠，其至少包括第一金属栅极，而没有变薄的含Si电极。

5. 发明申请

US20070138563A1 Dual metal gate self-aligned integration 有权
标题翻译：双金属栅极自对准集成
公开(公告)号：US20070138563A1
公开(公告)日：2007-06-21
申请号：US11303715
申请日：2005-12-16
申请人： Alessandro Callegari , Michael Chudzik , Bruce Doris , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen
发明人： Alessandro Callegari , Michael Chudzik , Bruce Doris , Vijay Narayanan , Vamsi Paruchuri , Michelle Steen
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L21/823842
摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.
摘要翻译：包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极提供电极。本发明还提供一种制造这种半导体结构的方法。

6. 发明申请

US20070173008A1 Introduction of metal impurity to change workfunction of conductive electrodes 有权
标题翻译：引入金属杂质来改变导电电极的功能
公开(公告)号：US20070173008A1
公开(公告)日：2007-07-26
申请号：US11336727
申请日：2006-01-20
申请人： Michael Chudzik , Bruce Doris , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Yun Wang , Keith Wong
发明人： Michael Chudzik , Bruce Doris , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Yun Wang , Keith Wong
IPC分类号： H01L21/8238
CPC分类号： H01L29/517 , H01L21/28088 , H01L21/823828 , H01L21/823857 , H01L29/4966 , H01L29/513 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures, such as, for example, field effect transistors (FETs) and/or metal-oxide-semiconductor capacitor (MOSCAPs), are provided in which the workfunction of a conductive electrode stack is changed by introducing metal impurities into a metal-containing material layer which, together with a conductive electrode, is present in the electrode stack. The choice of metal impurities depends on whether the electrode is to have an n-type workfunction or a p-type workfunction. The present invention also provides a method of fabricating such semiconductor structures. The introduction of metal impurities can be achieved by codeposition of a layer containing both a metal-containing material and workfunction altering metal impurities, forming a stack in which a layer of metal impurities is present between layers of a metal-containing material, or by forming a material layer including the metal impurities above and/or below a metal-containing material and then heating the structure so that the metal impurities are introduced into the metal-containing material.
摘要翻译：提供半导体结构，例如场效应晶体管（FET）和/或金属氧化物半导体电容器（MOSCAP），其中通过将金属杂质引入到含金属的物质中来改变导电电极堆叠的功函数材料层与导电电极一起存在于电极堆叠中。金属杂质的选择取决于电极是否具有n型功函数或p型功函数。本发明还提供一种制造这种半导体结构的方法。金属杂质的引入可以通过共沉积含有金属的材料和改变金属杂质的功函数的层来形成，形成其中金属杂质层存在于含金属材料的层之间的叠层，或通过形成包括在含金属材料上方和/或下面的金属杂质的材料层，然后加热该结构，使得金属杂质被引入到含金属的材料中。

7. 发明授权

US09768055B2 Isolation regions for SOI devices 有权
公开(公告)号：US09768055B2
公开(公告)日：2017-09-19
申请号：US13590836
申请日：2012-08-21
申请人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
发明人： Qing Liu , Nicolas Loubet , Prasanna Khare , Shom Ponoth , Maud Vinet , Bruce Doris
IPC分类号： H01L21/76 , H01L21/762 , H01L29/66 , H01L29/786
CPC分类号： H01L21/76232 , H01L29/66772 , H01L29/78654
摘要： An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

8. 发明授权

US09281247B2 Strained silicon and strained silicon germanium on insulator field-effect transistor 有权
标题翻译：应变硅和应变硅锗绝缘体上的场效应晶体管
公开(公告)号：US09281247B2
公开(公告)日：2016-03-08
申请号：US13615016
申请日：2012-09-13
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Devendra K. Sadana
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Devendra K. Sadana
IPC分类号： G03F1/36 , H01L21/84 , H01L21/8238 , H01L27/12
CPC分类号： H01L21/823807 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： A structure includes a tensilely strained NFET region including a strained silicon layer of a silicon on insulator wafer. A relaxed NFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer. A compressively strained PFET region includes a SiGe layer which was converted from a tensilely strained silicon layer of the silicon on insulator wafer. A relaxed PFET region includes one of an ion implanted silicon and an ion implanted silicon dioxide interface layer of a tensilely strained silicon layer of the silicon on insulator wafer.
摘要翻译：结构包括拉伸应变NFET区域，其包括绝缘体上硅晶片上的应变硅层。松弛NFET区域包括离子注入硅和绝缘硅晶片上的拉伸应变硅层的离子注入二氧化硅界面层之一。压缩应变PFET区域包括从绝缘体硅晶片的拉伸应变硅层转换的SiGe层。松弛PFET区域包括离子注入硅和绝缘硅晶片上的拉伸应变硅层的离子注入二氧化硅界面层之一。

9. 发明授权

US08890245B2 Raised source/drain structure for enhanced strain coupling from stress liner 有权
标题翻译：用于增强应力衬垫的应变耦合的源/漏结构
公开(公告)号：US08890245B2
公开(公告)日：2014-11-18
申请号：US13570833
申请日：2012-08-09
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam Shahidi
IPC分类号： H01L29/78 , H01L29/786 , H01L29/66 , H01L21/762
CPC分类号： H01L29/78654 , H01L21/76283 , H01L29/66772 , H01L29/78618
摘要： A transistor is provided that includes a buried oxide layer above a substrate. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer, the gate stack including a high-k oxide layer on the silicon layer and a metal gate on the high-k oxide layer. A nitride liner is adjacent to the gate stack. An oxide liner is adjacent to the nitride liner. A set of faceted raised source/drain regions having a part including a portion of the silicon layer. The set of faceted raised source/drain regions also include a first faceted side portion and a second faceted side portion.
摘要翻译：提供一种晶体管，其包括衬底上方的掩埋氧化物层。硅层在掩埋氧化物层之上。栅极堆叠在硅层上，栅极堆叠包括硅层上的高k氧化物层和高k氧化物层上的金属栅极。氮化物衬垫与栅堆叠相邻。氧化物衬垫与氮化物衬垫相邻。一组具有包括硅层的一部分的部分的凸起的源/漏区。所述一组切面隆起的源极/漏极区域还包括第一分面侧部分和第二分面侧部分。

10. 发明授权

US08691650B2 MOSFET with recessed channel film and abrupt junctions 有权
标题翻译：具有凹槽通道膜和突点的MOSFET
公开(公告)号：US08691650B2
公开(公告)日：2014-04-08
申请号：US13086459
申请日：2011-04-14
申请人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/336
CPC分类号： H01L29/0603 , H01L29/1054 , H01L29/4236 , H01L29/66545 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66651 , H01L29/66772 , H01L29/78
摘要： MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
摘要翻译：公开了用于制造具有凹陷沟道和突然结的MOSFET的MOSFET和方法。该方法包括在虚拟门就位的情况下创建源极和漏极扩展。源极/漏极延伸部分产生与硅衬底的扩散结。该方法通过去除伪栅极并蚀刻硅衬底中的凹槽来继续。凹部与源极和漏极结的至少一部分相交。然后，通过生长硅膜以至少部分地填充凹部而形成通道。该通道与源极和漏极具有尖锐的结，而沟道下方的未蚀刻的硅具有与源极和漏极的扩散结。因此，可以产生在相同晶体管中具有两个结区的尖锐和扩散的MOSFET。

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