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1. 发明授权

US07022603B2 Method for fabricating semiconductor device having stacked-gate structure 有权
标题翻译：具有层叠栅结构的半导体器件的制造方法
公开(公告)号：US07022603B2
公开(公告)日：2006-04-04
申请号：US10683612
申请日：2003-10-10
申请人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
发明人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
IPC分类号： H01L21/44
CPC分类号： H01L21/28052 , H01L29/4933
摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
摘要翻译：一种半导体制造方法，该半导体器件具有堆叠栅极结构。通过介电层与衬底绝缘的衬底上形成多晶硅层。在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。使用氮气和氢气对氮化钨层进行退火。依次形成覆盖氮化钨层的钨层和覆盖层。

2. 发明申请

US20050124127A1 Method for manufacturing gate structure for use in semiconductor device 审中-公开
标题翻译：制造用于半导体器件的栅极结构的方法
公开(公告)号：US20050124127A1
公开(公告)日：2005-06-09
申请号：US10726500
申请日：2003-12-04
申请人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
发明人： Tzu-En Ho , Chang-Rong Wu , Yi-Nan Chen , Kuo-Chien Wu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L21/4763 , H01L29/49 , H01L29/51
CPC分类号： H01L29/4933 , H01L21/28052 , H01L29/51 , H01L29/517 , H01L29/518
摘要： The present invention provides a method for manufacturing a stacked gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer, and a tungsten layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上依次形成栅极电介质层，多晶硅层，金属层，势垒层和钨层，在氮气环境中进行快速热退火（RTA）在所述钨层上形成氮化硅层，并将所述多层薄膜结构图案化为规定的形态。

3. 发明申请

US20050074957A1 Methods for manufacturing stacked gate structure and field effect transistor povided with the same 有权
标题翻译：堆叠栅极结构和场效应晶体管的制造方法相同
公开(公告)号：US20050074957A1
公开(公告)日：2005-04-07
申请号：US10864320
申请日：2004-06-10
申请人： Tzu-En Ho , Chang-Rong Wu
发明人： Tzu-En Ho , Chang-Rong Wu
IPC分类号： H01L21/00 , H01L21/28 , H01L21/336 , H01L29/49 , H01L29/78
CPC分类号： H01L29/7833 , H01L21/28061 , H01L29/4933
摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上依次形成栅介质层，多晶硅层，钛层和WNX层，在氮气环境中进行快速热退火（RTA），形成氮化硅层，并且将多层薄膜结构图案化成预定的构造。

4. 发明授权

US06858516B2 Manufacturing method of a high aspect ratio shallow trench isolation region 有权
标题翻译：高深宽比浅沟槽隔离区的制造方法
公开(公告)号：US06858516B2
公开(公告)日：2005-02-22
申请号：US10279511
申请日：2002-10-23
申请人： Tzu-En Ho , Chang Rong Wu , Hsin-Jung Ho
发明人： Tzu-En Ho , Chang Rong Wu , Hsin-Jung Ho
IPC分类号： H01L21/762 , H01L21/8242 , H01L21/76
CPC分类号： H01L21/76224
摘要： A manufacturing method of a high aspect ratio shallow trench isolation region. A substrate with a trench therein is provided and placed into a chamber. A first insulation layer is formed on the substrate as well as inside the trench by high density plasma chemical vapor deposition. The majority of the first insulation layer outside the trench is removed by in situ etching using carbon fluoride as an etching gas with high selectivity for SiO2/SiN etching ratio, and a second insulation layer is formed on the first insulation layer by high density plasma chemical vapor deposition, filling the trench. According to the present invention, a high aspect ratio shallow trench isolation region without voids can thus be achieved.
摘要翻译：高宽比浅沟槽隔离区域的制造方法。提供其中具有沟槽的衬底并将其放置在室中。第一绝缘层通过高密度等离子体化学气相沉积形成在衬底上以及沟内。通过使用氟化碳作为蚀刻气体的原位蚀刻除去沟槽外部的第一绝缘层的大部分，对SiO 2 / SiN蚀刻比率具有高选择性，并且通过高密度等离子体化学品在第一绝缘层上形成第二绝缘层气相沉积，填充沟槽。根据本发明，可以实现无空隙的高纵横比浅沟槽隔离区域。

5. 发明授权

US07101777B2 Methods for manufacturing stacked gate structure and field effect transistor provided with the same 有权
标题翻译：制造堆叠栅极结构的方法和具有该栅极结构的场效应晶体管
公开(公告)号：US07101777B2
公开(公告)日：2006-09-05
申请号：US10864320
申请日：2004-06-10
申请人： Tzu-En Ho , Chang-Rong Wu
发明人： Tzu-En Ho , Chang-Rong Wu
IPC分类号： H01L21/3205
CPC分类号： H01L29/7833 , H01L21/28061 , H01L29/4933
摘要： The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a titanium layer, and a WNX layer on a semiconductor substrate, carrying out a rapid thermal annealing (RTA) in a nitrogen ambient, forming a silicon nitride layer on the tungsten layer, and patterning the multilayer thin-film structure into a predetermined configuration.
摘要翻译：本发明提供一种在半导体器件中制造堆叠栅极结构的方法。该方法包括以下步骤：在半导体衬底上顺序地形成栅介质层，多晶硅层，钛层和WN层，并进行快速热退火（RTA）氮气环境，在钨层上形成氮化硅层，并将多层薄膜结构图案化成预定的构型。

6. 发明申请

US20060134913A1 Method for fabricating semiconductor device having stacked-gate structure 有权
公开(公告)号：US20060134913A1
公开(公告)日：2006-06-22
申请号：US11338579
申请日：2006-01-23
申请人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
发明人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
IPC分类号： H01L21/44 , H01L21/302
CPC分类号： H01L21/28052 , H01L29/4933
摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.

7. 发明授权

US06958283B2 Method for fabricating trench isolation 有权
公开(公告)号：US06958283B2
公开(公告)日：2005-10-25
申请号：US10690859
申请日：2003-10-22
申请人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
发明人： Chien-Mao Liao , Tzu-En Ho , Chang-Rong Wu , Chih-How Chang , Sheng-Wei Yang , Sheng-Tsung Chen , Chung-Yuan Lee , Wen-Sheng Liao , Chen-Chou Huang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method for forming a trench isolation. A semiconductor substrate with an opening is provided, on which a mask layer is formed. A first insulating layer is conformably formed on the semiconductor substrate and the trench, and the trench is filled with the first insulating layer. The first insulating layer is anisotropically etched to below the semiconductor substrate. A second insulating layer is formed on the semiconductor substrate and the trench. The second insulating layer is planarized to expose the mask layer.

8. 发明申请

US20050020044A1 Method for fabricating semiconductor device having stacked-gate structure 有权
标题翻译：具有层叠栅结构的半导体器件的制造方法
公开(公告)号：US20050020044A1
公开(公告)日：2005-01-27
申请号：US10683612
申请日：2003-10-10
申请人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
发明人： Tzu-En Ho , Chih-Hao Chang , Chang-Rong Wu , Kuo-Hui Su
IPC分类号： H01L21/28 , H01L21/4763 , H01L29/49
CPC分类号： H01L21/28052 , H01L29/4933
摘要： A method for fabricating a semiconductor a semiconductor device having a stacked-gate structure. A polysilicon layer is formed overlying a substrate, which is insulated from the substrate by a dielectric layer. A metal-flash layer is formed overlying the polysilicon layer, and then a tungsten nitride layer is formed overlying the titanium layer. The tungsten nitride layer is annealed using nitrogen and hydrogen gases. A tungsten layer and a cap layer are successively formed overlying the tungsten nitride layer.
摘要翻译：一种半导体制造方法，该半导体器件具有堆叠栅极结构。通过介电层与衬底绝缘的衬底上形成多晶硅层。在多晶硅层上形成金属闪光层，然后在钛层上形成氮化钨层。使用氮气和氢气对氮化钨层进行退火。依次形成覆盖氮化钨层的钨层和覆盖层。

9. 发明授权

US06794270B2 Method for shallow trench isolation fabrication and partial oxide layer removal 有权
标题翻译：浅沟槽隔离制造和部分氧化物层去除的方法
公开(公告)号：US06794270B2
公开(公告)日：2004-09-21
申请号：US10394681
申请日：2003-03-21
申请人： Pei-Ing Lee , Chang Rong Wu , Tzu En Ho , Yi-Nan Chen , Hsien Wen Su
发明人： Pei-Ing Lee , Chang Rong Wu , Tzu En Ho , Yi-Nan Chen , Hsien Wen Su
IPC分类号： H01L2176
CPC分类号： H01L21/31055 , H01L21/31133 , H01L21/31144 , H01L21/76224
摘要： A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.
摘要翻译：一种形成完全沉积的浅沟槽隔离的方法。第一氧化物层在半导体衬底的表面上以及纵横比大于3的沟槽上共形地形成。通过旋转喷涂将液体蚀刻屏蔽填充在沟槽中以覆盖沟槽中的氧化物层。然后将蚀刻剂喷射到半导体衬底的表面上以去除未覆盖的氧化物层并暴露半导体衬底的表面。蚀刻剂的密度小于液体蚀刻屏蔽层的密度。第二氧化物层沉积在沟槽中以形成无空隙或接缝的隔离。

10. 发明授权

US06743728B2 Method for forming shallow trench isolation 有权
标题翻译：形成浅沟槽隔离的方法
公开(公告)号：US06743728B2
公开(公告)日：2004-06-01
申请号：US10322224
申请日：2002-12-17
申请人： Tzu En Ho , Chang Rong Wu , Tung-Wang Huang , Shing-Yih Shih
发明人： Tzu En Ho , Chang Rong Wu , Tung-Wang Huang , Shing-Yih Shih
IPC分类号： H01L21301
CPC分类号： H01L21/76224 , H01L21/02129 , H01L21/02274 , H01L21/31051 , H01L21/31612 , H01L21/31625
摘要： A method for forming shallow trench isolation. A substrate is provided with a mask layer formed thereon. The mask layer is etched to expose a portion of the substrate, and the portion of the substrate is etched to form a trench. A liner layer is formed on the inside wall of the trench. A first dielectric layer and a sacrificial layer are sequentially deposited on the substrate such that the trench is substantially filled, wherein the first dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). Portions of the first dielectric layer and the sacrificial layer are removed from the trench. A second dielectric layer is deposited on the substrate such that the trench is substantially filled, wherein the second dielectric layer is formed by high density plasma chemical vapor deposition (HDPCVD). A portion of the second dielectric layer is removed from the trench.
摘要翻译：一种形成浅沟槽隔离的方法。衬底上形成有掩模层。蚀刻掩模层以暴露衬底的一部分，并蚀刻衬底的该部分以形成沟槽。衬垫层形成在沟槽的内壁上。第一电介质层和牺牲层顺序地沉积在衬底上，使得沟槽基本上被填充，其中第一介电层通过高密度等离子体化学气相沉积（HDPCVD）形成。第一电介质层和牺牲层的一部分从沟槽中去除。第二电介质层沉积在衬底上，使得沟槽基本上被填充，其中第二电介质层通过高密度等离子体化学气相沉积（HDPCVD）形成。第二电介质层的一部分从沟槽去除。

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