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1. 发明授权

US07522458B2 Memory and method of controlling access to memory 失效
标题翻译：控制内存访问的内存和方法
公开(公告)号：US07522458B2
公开(公告)日：2009-04-21
申请号：US11535703
申请日：2006-09-27
申请人： Toshio Sunaga , Hisatada Miyatake
发明人： Toshio Sunaga , Hisatada Miyatake
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/22 , G11C7/222 , G11C11/406 , G11C11/40615 , G11C11/4076
摘要： A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.
摘要翻译：存储器，包括至少一个存储单元阵列和用于控制对存储器阵列的访问的访问控制电路。访问控制电路包括接收第一（CE）和第二（ADV）输入信号的访问命令电路（ADRCTL），并且输出允许开始存储器访问的访问命令信号（ACMDS）和命令识别电路（CMDDEC）接收第一（CE）和第二（ADV）输入信号，第三（OE）和第四（WE）输入信号以及时钟信号（CLK）），并输出指令判别信号（WRITE）访问命令信号用于读取操作或写入操作。

2. 发明授权

US07518942B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07518942B2
公开(公告)日：2009-04-14
申请号：US11555333
申请日：2006-11-01
申请人： Toshio Sunaga
发明人： Toshio Sunaga
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/08 , G11C7/1072 , G11C7/22 , G11C8/12 , G11C11/4076 , G11C11/4087 , G11C11/4091
摘要： The objective of the present invention is to provide a semiconductor storage device wherein a low active current is obtained by reducing the number of sense amplifiers to be activated at a time. An SDRAM has a divided word line structure, and includes a plurality of banks, each of which includes arrays AR1 to AR64 and 4K main word lines MWL. A row address signal is fetched in response to a row address strobe signal, and a segment address signal is fetched in response to a column address strobe signal. A main row decoder MRD activates main word lines MWL1, MWL5, MWL9 and MWL13 in response to the row address signal, and a segment row decoder SRD selects only an array AR1 in response to a segment address signal, and activates only 1K sense amplifiers SA corresponding to the selected array AR. When the main word lines MWL1, MWL5, MWL9 and MWL13 are activated, the segment word lines in arrays AR2 to AR64 are not activated, so that data are not destroyed.
摘要翻译：本发明的目的是提供一种半导体存储装置，其中通过减少一次要激活的读出放大器的数量来获得低有功电流。 SDRAM具有划分的字线结构，并且包括多个存储体，每个存储体包括阵列AR1至AR64和4K主字线MWL。响应于行地址选通信号取出行地址信号，响应于列地址选通信号取出段地址信号。主行解码器MRD响应于行地址信号激活主字线MWL1，MWL5，MWL9和MWL13，并且段行解码器SRD响应于段地址信号仅选择阵列AR1，并且仅激活1K个读出放大器SA 对应于所选阵列AR。当主字线MWL1，MWL5，MWL9和MWL13被激活时，阵列AR2到AR64中的段字线不被激活，使得数据不被破坏。

3. 发明授权

US07460420B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07460420B2
公开(公告)日：2008-12-02
申请号：US11553617
申请日：2006-10-27
申请人： Toshio Sunaga
发明人： Toshio Sunaga
IPC分类号： G11C7/00
CPC分类号： G11C11/408 , G11C29/806
摘要： The objective of the present invention is to provide a DRAM that reduces the current consumed by an address comparison circuit that compares an address signal with a defective address signal that has been programmed. Redundant predecoders predecode a defective row address signal DRA output by program circuits, and an address comparison circuit compares a predecoded signal, output by a predecoder, with the defective predecoded signals PDRA, output by the redundant predecoders. In the case of a 2-bit predecoding system, the address comparison circuit compares the predecoded signal PRA with the defective predecoded signal PDRA using four bits in order to compare the row address signal RA with the defective row address signal DRA using groups of two bits.
摘要翻译：本发明的目的是提供一种DRAM，其减少地址比较电路消耗的电流，该地址比较电路将地址信号与已编程的缺陷地址信号进行比较。冗余预解码器预编码由编程电路输出的有缺陷的行地址信号DRA，并且地址比较电路将由预解码器输出的预解码信号与由冗余预解码器输出的缺陷预解码信号PDRA进行比较。在2位预解码系统的情况下，地址比较电路使用四位比较预解码信号PRA和缺陷预解码信号PDRA，以便使用两位组来比较行地址信号RA与缺陷行地址信号DRA 。

4. 发明授权

US07349235B2 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US07349235B2
公开(公告)日：2008-03-25
申请号：US11381578
申请日：2006-05-04
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C5/08
CPC分类号： G11C11/16
摘要： A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.
摘要翻译：根据一个实施例的非易失性存储器件包括多个存储单元，每个存储单元包括磁阻元件和选择晶体管，其中存储单元被布置成二维阵列。第一互连线在存储器阵列的第一方向上延伸，并且用作包含在每个存储单元中的选择晶体管的栅电极。第二互连线在存储器阵列的第一方向上延伸。第三互连线在第二方向上延伸。至少一些存储单元的磁电阻元件夹在第二和第三互连线之间。

5. 发明授权

US07123110B2 Low power self refresh timer oscillator 失效
标题翻译：低功耗自刷新定时器振荡器
公开(公告)号：US07123110B2
公开(公告)日：2006-10-17
申请号：US10904127
申请日：2004-10-25
申请人： Toshio Sunaga , Takeo Yasuda
发明人： Toshio Sunaga , Takeo Yasuda
IPC分类号： H03K3/02 , H03K7/00
CPC分类号： H03K3/0231
摘要： A low power oscillator circuit for a self-refresh timer in a memory array is disclosed. When a voltage (V1) of a comparison node (N1) exceeds a first reference voltage (Vref1), a differential amplifier (101) in an oscillator (1) causes a pulse generator (110) to output a pulse. A charge/discharge circuit (105) discharges the comparison node (N1) in response to pulse. In this event, a control circuit (4) disables a first control signal (CT1) to halt operation of the differential amplifier (101). When the voltage (V1) exceeds a second reference voltage (Vref2) equivalent to the sum of threshold voltages of a discharge circuit (43) in consequence of gradually charging the comparison node (N1) by the charge/discharge circuit (105) after it was discharged, the control circuit (4) activates the first control signal (CT1) to operate the differential amplifier (101).
摘要翻译：公开了一种用于存储器阵列中的自刷新定时器的低功率振荡器电路。当比较节点（N1）的电压（V 1）超过第一参考电压（Vref 1）时，振荡器（1）中的差分放大器（101）使得脉冲发生器（110）输出脉冲。充电/放电电路（105）响应于脉冲放电比较节点（N1）。在这种情况下，控制电路（4）禁止第一控制信号（CT1）停止差分放大器（101）的操作。当电压（V 1）超过与放电电路（43）的阈值电压之和相等的第二参考电压（Vref 2）时，结果是由充电/放电电路（105）逐渐对比较节点（N1）充电），控制电路（4）激活第一控制信号（CT1）以操作差分放大器（101）。

6. 发明授权

US06925028B2 DRAM with multiple virtual bank architecture for random row access 失效
标题翻译：具有多个虚拟银行架构的DRAM用于随机行访问
公开(公告)号：US06925028B2
公开(公告)日：2005-08-02
申请号：US10473632
申请日：2002-03-06
申请人： Kohji Hosokawa , Toshio Sunaga , Shinpei Watanabe
发明人： Kohji Hosokawa , Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C11/401 , G11C11/407 , G11C11/408 , G11C11/4097 , G11C8/00
CPC分类号： G11C7/1066 , G11C11/408 , G11C11/4087 , G11C11/4097
摘要： A DRAM and access method for DRAM with a high data rate in a random row access mode. The DRAM includes a plurality of memory blocks composed of a plurality of storage segments each with a series of main word lines and sub-word lines. Each memory block is decoded into multiple segments and the main word lines are activated to select a predetermined number of sub-word lines. A corner block is provided that contains a plurality of Z-lines for selecting one of the sub-wordlines and a plurality of segment select lines for selecting a specific memory segment by activating a local Z-line.
摘要翻译：一种具有随机行访问模式的高数据速率的DRAM的DRAM和存取方法。 DRAM包括由多个存储段组成的多个存储块，每个存储段具有一系列主字线和子字线。每个存储块被解码成多个段，并且主字线被激活以选择预定数量的子字线。提供了一个角块，其包含用于选择子字线之一的多条Z线和用于通过激活本地Z线来选择特定存储器段的多个段选择线。

7. 发明申请

US20050073897A1 Non-volatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US20050073897A1
公开(公告)日：2005-04-07
申请号：US10964352
申请日：2004-10-12
申请人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
发明人： Hisatada Miyatake , Kohki Noda , Toshio Sunaga , Hiroshi Umezaki , Hideo Asano , Koji Kitamura
IPC分类号： G11C11/14 , G11C11/15 , G11C11/16 , H01L21/8246 , H01L27/105 , H01L43/08 , G11C11/00
CPC分类号： G11C11/16
摘要： MRAM has read word lines WLR and write word line WLW extending in the y direction, write/read bit line BLW/R and write bit line BLW extending in the x direction, and the memory cells MC disposed at the points of the intersection of these lines. The memory MC includes sub-cells SC1 and SC2. The sub-cell SC1 includes magneto resistive elements MTJ1 and MTJ2 and a selection transistor Tr1, and the sub-cell SC2 includes magneto resistive elements MTJ3 and MTJ4 and a selection transistor Tr2. The magneto resistive elements MTJ1 and MTJ2 are connected in parallel, and the magneto resistive elements MTJ3 and MTJ4 are also connected in parallel. Further, the sub-cells SC1 and SC2 are connected in series between the write/read bit line BLW/R and the ground.
摘要翻译： MRAM具有在y方向上延伸的字线WLR和写入字线WLW，在x方向上延伸的写入/读取位线BLW / R和写入位线BLW，以及设置在这些交点处的存储单元MC 线条。存储器MC包括子单元SC1和SC2。子单元SC1包括磁阻元件MTJ1和MTJ2以及选择晶体管Tr1，子单元SC2包括磁阻元件MTJ3和MTJ4以及选择晶体管Tr2。磁电阻元件MTJ1和MTJ2并联连接，磁电阻元件MTJ3和MTJ4也并联连接。此外，子单元SC1和SC2串联连接在写/读位线BLW / R和地之间。

8. 发明授权

US06785154B2 MRAM and access method thereof 有权
标题翻译： MRAM及其访问方法
公开(公告)号：US06785154B2
公开(公告)日：2004-08-31
申请号：US10134100
申请日：2002-04-26
申请人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura , Hideo Asano , Kohki Noda , Hiroshi Umezaki
发明人： Toshio Sunaga , Hisatada Miyatake , Koji Kitamura , Hideo Asano , Kohki Noda , Hiroshi Umezaki
IPC分类号： G11C1700
CPC分类号： G11C11/15 , G11C2207/2263
摘要： A magnetic random access memory (MRAM) circuit block and access method thereof are disclosed herein which includes a circuit for sensing a data write current passing through a bitline 32 and, for generating a stop signal for stopping a data write current supply to the bitline 32 and a write wordline 30 after data is written in an magnetic tunnel junction (MTJ) element 44. Further, when data to be written to the storage element is the same as the data already stored therein, no write current is supplied to the write wordline 30, thereby saving power.
摘要翻译：本文公开了磁性随机存取存储器（MRAM）电路块及其访问方法，其包括用于感测通过位线32的数据写入电流的电路，并且用于产生用于停止向位线32的数据写入电流供应的停止信号以及数据写入磁性隧道结（MTJ）元件44之后的写入字线30.此外，当要写入存储元件的数据与已经存储的数据相同时，不向写入字线提供写入电流 30，从而节省电力。

9. 发明授权

US06545932B1 SDRAM and method for data accesses of SDRAM 失效
标题翻译： SDRAM和SDRAM数据访问方法
公开(公告)号：US06545932B1
公开(公告)日：2003-04-08
申请号：US09452408
申请日：1999-12-01
申请人： Toshio Sunaga , Shinpei Watanabe
发明人： Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1018
摘要： An SRAM which eliminates any seam in consecutive read/write data flows when the burst-length is short, thus making it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks. This operation enables the band-width of SDRAM to approximate the data transmission rate at the peak moment determined by the maximum frequency of the clock.
摘要翻译：当脉冲串长度短时，SRAM能够消除连续读/写数据流中的任何接缝，从而使得能够实现针对不同行地址之间的数据的突发模式的无缝访问。该操作使SDRAM的带宽能够在由时钟的最大频率确定的峰值时刻近似数据传输速率。

10. 发明授权

US5745424A Method for transferring data bit for DRAM 失效
标题翻译：用于传送DRAM数据位的方法
公开(公告)号：US5745424A
公开(公告)日：1998-04-28
申请号：US587428
申请日：1996-01-17
申请人： Minoru Furuta , Toshio Sunaga
发明人： Minoru Furuta , Toshio Sunaga
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/407
CPC分类号： G11C7/1018
摘要： A DRAM access system is provided which can maintain high speed as in the burst DRAM, and can perform addressing by burst transfer unit as in the synchronous DRAM, and also have high compatibility with the conventional transfer system.
摘要翻译：提供了DRAM存取系统，其可以如突发DRAM中那样保持高速度，并且可以像在同步DRAM中那样执行突发传送单元的寻址，并且与传统的传输系统具有高的兼容性。

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