专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5745424A Method for transferring data bit for DRAM 失效
标题翻译：用于传送DRAM数据位的方法
公开(公告)号：US5745424A
公开(公告)日：1998-04-28
申请号：US587428
申请日：1996-01-17
申请人： Minoru Furuta , Toshio Sunaga
发明人： Minoru Furuta , Toshio Sunaga
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C11/407
CPC分类号： G11C7/1018
摘要： A DRAM access system is provided which can maintain high speed as in the burst DRAM, and can perform addressing by burst transfer unit as in the synchronous DRAM, and also have high compatibility with the conventional transfer system.
摘要翻译：提供了DRAM存取系统，其可以如突发DRAM中那样保持高速度，并且可以像在同步DRAM中那样执行突发传送单元的寻址，并且与传统的传输系统具有高的兼容性。

2. 发明授权

US5134389A Display terminal device 失效
标题翻译：显示终端设备
公开(公告)号：US5134389A
公开(公告)日：1992-07-28
申请号：US473490
申请日：1990-02-01
申请人： Minoru Furuta , Manabu Furuya
发明人： Minoru Furuta , Manabu Furuya
IPC分类号： G06F3/041 , G06F3/033 , G06F3/037 , G06F3/038 , G06F3/048
CPC分类号： G06F3/0383
摘要： A display terminal and apparatus for detecting the position of a light pen detecting field on a display surface at times the light pen is pointed to the light pen detecting field is described incorporating a column counter, scanning line counter, character row counter, light pen detecting field counter, and a light pen detecting line counter interconnected with an address generator, decoder, character code buffer, attribute buffer, font memory, light pen detection line generator mask line generator and scanning type display device. The invention overcomes the problem of misjudging the column address arising from variable delay times of the sensor signal from a light pen pointed to and sensing light from a display surface.

3. 发明授权

US5893158A Multibank dram system controlled by multiple dram controllers with an active bank detector 失效
标题翻译：由多个具有活动银行检测器的控制器控制的多银行系统
公开(公告)号：US5893158A
公开(公告)日：1999-04-06
申请号：US762119
申请日：1996-12-09
申请人： Minoru Furuta
发明人： Minoru Furuta
IPC分类号： G11C11/407 , G06F12/06 , G06F13/16 , G11C8/12 , G11C11/401 , G11C11/408 , G06F12/14
CPC分类号： G06F13/1647 , G11C11/4087 , G11C8/12
摘要： In the control of DRAM having a plurality of banks by a pair of memory controllers, a high rate operation is enabled by a pipeline control even during an exchange of the privilege to use a memory. Specifically, a system memory 11 having a plurality of banks is shared by a memory controller 12 and an external device 13 for pipeline control. Both the memory controller 12 and the external device 13 include a monitor circuit which monitors an address and a control signal delivered by the counterpart. When the privilege to use a memory is to be transferred, a bank which is currently active is examined, and such access is immediately allowed when the access is to a bank which is not active. When the access is to a bank which is currently active, a standby interval is provided, and the access is allowed after its transition to an inactive condition. A pipeline control is enabled even during a changeover of the privilege to use the memory, thus allowing a high rate operation of a computer system.
摘要翻译：在通过一对存储器控制器控制具有多个存储体的DRAM时，即使在交换存储器的特权时，通过流水线控制实现高速率操作。具体地说，具有多个存储体的系统存储器11被存储器控制器12和用于流水线控制的外部装置13共享。存储器控制器12和外部装置13都包括监视电路，监视器电路监视对方发送的地址和控制信号。当要传送使用存储器的权限时，检查当前处于活动状态的存储体，并且当访问到不活动的存储体时，立即允许这种访问。当访问当前处于活动状态的存储区时，提供备用间隔，并且在转换到非活动状态之后允许访问。甚至在切换使用存储器的特权期间也启用管线控制，从而允许计算机系统的高速率操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式