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1. 发明授权

US06977857B2 DRAM and refresh method thereof 失效
标题翻译： DRAM及其刷新方法
公开(公告)号：US06977857B2
公开(公告)日：2005-12-20
申请号：US10446400
申请日：2003-05-28
申请人： Masaya Mori , Toshio Sunaga , Shinpei Watanabe
发明人： Masaya Mori , Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061 , G11C2211/4067
摘要： The present invention relates to a DRAM having a memory array that is divided into a plurality of memory blocks. A memory block having a long data retention time is selected from the plurality of memory blocks and a logical address is allocated to the selected memory block. The selected memory block is refreshed at longer time intervals compared to conventional DRAMs resulting in lower power consumption.
摘要翻译：本发明涉及具有被划分成多个存储块的存储器阵列的DRAM。从多个存储块中选择具有长数据保持时间的存储块，并且将逻辑地址分配给所选存储块。与常规DRAM相比，所选择的存储器块以更长的时间间隔被刷新，导致较低的功耗。

2. 发明授权

US06650573B2 Data input/output method 失效
公开(公告)号：US06650573B2
公开(公告)日：2003-11-18
申请号：US10063059
申请日：2002-03-15
申请人： Toshio Sunaga , Shinpei Watanabe
发明人： Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C700
CPC分类号： G11C7/1087 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C11/4093
摘要： The present invention discloses a method for data input/output for memory which minimizes losses of data interruption when switching between reading and writing. A method for data input/output comprises the steps of: holding predetermined data from memory array 12 upon m-th (m is integer) read command; outputting the predetermined data to common I/O 30 and holding new data from memory array 12 upon (m+1)-th read command; holding predetermined data from common I/O 30 upon n-th (n is integer) write command; and storing the predetermined data in memory array 12 and holding new data from common I/O 30 upon (n+1)-th write command.

3. 发明授权

US06925028B2 DRAM with multiple virtual bank architecture for random row access 失效
标题翻译：具有多个虚拟银行架构的DRAM用于随机行访问
公开(公告)号：US06925028B2
公开(公告)日：2005-08-02
申请号：US10473632
申请日：2002-03-06
申请人： Kohji Hosokawa , Toshio Sunaga , Shinpei Watanabe
发明人： Kohji Hosokawa , Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C11/401 , G11C11/407 , G11C11/408 , G11C11/4097 , G11C8/00
CPC分类号： G11C7/1066 , G11C11/408 , G11C11/4087 , G11C11/4097
摘要： A DRAM and access method for DRAM with a high data rate in a random row access mode. The DRAM includes a plurality of memory blocks composed of a plurality of storage segments each with a series of main word lines and sub-word lines. Each memory block is decoded into multiple segments and the main word lines are activated to select a predetermined number of sub-word lines. A corner block is provided that contains a plurality of Z-lines for selecting one of the sub-wordlines and a plurality of segment select lines for selecting a specific memory segment by activating a local Z-line.
摘要翻译：一种具有随机行访问模式的高数据速率的DRAM的DRAM和存取方法。 DRAM包括由多个存储段组成的多个存储块，每个存储段具有一系列主字线和子字线。每个存储块被解码成多个段，并且主字线被激活以选择预定数量的子字线。提供了一个角块，其包含用于选择子字线之一的多条Z线和用于通过激活本地Z线来选择特定存储器段的多个段选择线。

4. 发明授权

US06545932B1 SDRAM and method for data accesses of SDRAM 失效
标题翻译： SDRAM和SDRAM数据访问方法
公开(公告)号：US06545932B1
公开(公告)日：2003-04-08
申请号：US09452408
申请日：1999-12-01
申请人： Toshio Sunaga , Shinpei Watanabe
发明人： Toshio Sunaga , Shinpei Watanabe
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1018
摘要： An SRAM which eliminates any seam in consecutive read/write data flows when the burst-length is short, thus making it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks. This operation enables the band-width of SDRAM to approximate the data transmission rate at the peak moment determined by the maximum frequency of the clock.
摘要翻译：当脉冲串长度短时，SRAM能够消除连续读/写数据流中的任何接缝，从而使得能够实现针对不同行地址之间的数据的突发模式的无缝访问。该操作使SDRAM的带宽能够在由时钟的最大频率确定的峰值时刻近似数据传输速率。

5. 发明授权

US06085300A DRAM system with simultaneous burst read and write 失效
标题翻译： DRAM系统具有同时突发读写功能
公开(公告)号：US06085300A
公开(公告)日：2000-07-04
申请号：US934034
申请日：1997-09-19
申请人： Toshio Sunaga , Shinpei Watanabe
发明人： Toshio Sunaga , Shinpei Watanabe
IPC分类号： G06F12/00 , G11C7/10 , G11C11/407 , G11C11/409 , G11C11/4096
CPC分类号： G11C7/1021 , G11C11/4096 , G11C7/1018 , G11C7/1051 , G11C7/1075 , G11C7/1078 , G11C7/1087 , G11C7/1093
摘要： A DRAM system is described that can prevent a substantial reduction in bandwidth with respect to a clock pulse frequency even when banks are accessed in no specific order. As a result, provided is a memory system constituted by DRAM whereby a seamless operation is assured not only for reading but also for writing.
摘要翻译：描述了一种DRAM系统，其可以防止相对于时钟脉冲频率的带宽的显着降低，即使当以不特定顺序访问存储体时。结果，提供了由DRAM构成的存储器系统，由此不仅可以确保无缝操作用于读取，而且可以确保写入。

6. 发明授权

US07469243B2 Method and device for searching fixed length data 失效
标题翻译：用于搜索固定长度数据的方法和设备
公开(公告)号：US07469243B2
公开(公告)日：2008-12-23
申请号：US10707943
申请日：2004-01-27
申请人： Masaya Mori , Shinpei Watanabe , Yoshihisa Takatsu , Toshio Sunaga
发明人： Masaya Mori , Shinpei Watanabe , Yoshihisa Takatsu , Toshio Sunaga
IPC分类号： G06F7/00 , G06F12/00 , G06F15/16
CPC分类号： G06F17/30949 , G06F7/02 , Y10S707/99933
摘要： Embodiments of the present invention provide method and device for searching fixed length data. The device includes a hash operation means for operating and outputting a hash value of inputted fixed length data, a data table memory consisting of N numbers of memory banks, where N is an integer that is more than and equal to 2, the data table memory for storing a data table holding a large number of fixed length data, a pointer table memory for storing a memory pointer table holding a memory address at which each fixed length datum is stored with the hash value as an index, and a comparison means for simultaneously comparing a plurality of fixed length data stored at the same memory address in the N numbers of memory banks with a single fixed length datum inputted to the hash operation means, the comparison means for outputting results of the comparison.
摘要翻译：本发明的实施例提供了用于搜索固定长度数据的方法和装置。该装置包括用于操作和输出输入的固定长度数据的散列值的散列操作装置，由N个存储体组成的数据表存储器，其中N是大于等于2的整数，数据表存储器用于存储保持大量固定长度数据的数据表;指针表存储器，用于存储存储指针表，该存储器指针表保存以散列值作为索引存储每个固定长度数据的存储器地址;以及比较装置，用于同时将存储在N个存储体组中的相同存储器地址的多个固定长度数据与输入到散列运算装置的单个固定长度数据进行比较，该比较装置用于输出比较结果。

7. 发明授权

US07124278B2 Information processing device and method, program, data structure, and computer-readable recording medium 失效
标题翻译：信息处理装置和方法，程序，数据结构和计算机可读记录介质
公开(公告)号：US07124278B2
公开(公告)日：2006-10-17
申请号：US10707941
申请日：2004-01-27
申请人： Masaya Mori , Shinpei Watanabe , Yoshihisa Takatsu , Toshio Sunaga
发明人： Masaya Mori , Shinpei Watanabe , Yoshihisa Takatsu , Toshio Sunaga
IPC分类号： G06F12/00
CPC分类号： G06F17/30949 , H04L29/12839 , H04L61/6022
摘要： Upon implementing a data registration into or a data retrieval from a data table (3) where first item data are registered along with corresponding second item data, there are used a first pointer table (1) where pointers to part of the registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a first hash function (6) to the first item data of the part of the registered data, and a second pointer table (2) where pointers to the other registered data in the data table are registered in storage positions that are designated by hash values obtained by applying a second hash function (22) to the first item data of the other registered data.
摘要翻译：在从第一项目数据与相应的第二项目数据一起登记的数据表（3）中实现数据注册或数据检索时，使用第一指针表（1），其中指向数据表被登记在由通过将第一散列函数（6）应用于登记数据的一部分的第一项数据而获得的散列值所指定的存储位置中，以及第二指针表（2），其中指向另一个寄存器的指针数据表中的数据被登记在通过将第二散列函数（22）应用于其他登记数据的第一项数据而获得的散列值所指定的存储位置中。

8. 发明授权

US06898661B2 Search memory, memory search controller, and memory search method 失效
标题翻译：搜索内存，内存搜索控制器和内存搜索方法
公开(公告)号：US06898661B2
公开(公告)日：2005-05-24
申请号：US10248781
申请日：2003-02-18
申请人： Masaya Mori , Toshio Sunaga , Shinpei Watanabe
发明人： Masaya Mori , Toshio Sunaga , Shinpei Watanabe
IPC分类号： G06F12/00 , G11C15/00 , G06F12/02
CPC分类号： G11C15/00 , Y10S707/99933
摘要： A distributor and a search controller are added to the memory. A search is performed with an algorithm such as quick search by repeating reading of memory cells, comparing of the reading result, and narrowing down of entries to be compared based on the comparison result. Performing this sequential processing in the memory provides valid data in a bus time plus about half of a cycle time required in repeating reading a conventional memory. Then, the latter half of the cycle time can be used for comparison, as well as generation of the next memory cell address, so that the search can be finished in a bus time multiplied by the number of repetitions of reading the memory cells plus one bus time. As a result, a CAM function can be achieved that allows for more than tens of thousands of entry data items, the number of which is equal to the size of DRAM divided by the number of banks, rather than hundreds or thousands of entry data items as conventional CAM.
摘要翻译：分配器和搜索控制器被添加到存储器中。基于比较结果，通过重复读取存储器单元，比较读取结果和缩小要比较的条目来进行快速搜索等算法的搜索。在存储器中执行这种顺序处理在总线时间内提供有效的数据加上重复读取常规存储器所需的周期时间的大约一半。然后，循环时间的后半部分可以用于比较，以及下一个存储单元地址的生成，使得可以在总线时间乘以读取存储器单元的重复次数加上一个公共汽车时间。结果，可以实现CAM功能，其允许数以万计的入口数据项，其数目等于DRAM的大小除以银行的数量，而不是数百或数千个条目数据项如传统CAM。

9. 发明授权

US06865136B2 Timing circuit and method of changing clock period 有权
标题翻译：定时电路及时钟周期改变方法
公开(公告)号：US06865136B2
公开(公告)日：2005-03-08
申请号：US10604057
申请日：2003-06-24
申请人： Toshio Sunaga , Shinpei Watanabe , Masaya Mori
发明人： Toshio Sunaga , Shinpei Watanabe , Masaya Mori
IPC分类号： G11C7/22 , G11C8/00 , G11C11/34 , G11C11/406
CPC分类号： G11C11/40626 , G11C7/04 , G11C7/22 , G11C7/222 , G11C11/406 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： The object of this invention is to provide a timing circuit that can change a clock period with low power consumption. The timing circuit includes a clock generator 11, comparators 12 and 13 for comparing an inputted control voltage TDV and reference voltages VR, respectively, retaining circuits 18 and 19 for retaining outputs of the comparators, respectively, and circuits 20, 21 and 22 for producing timing pulses TDT as an output thereof based on outputs of the retaining circuits and clock signals outputted from the clock generator. Each comparator receives a first clock signal SS outputted from the clock generator and is operated only for a time corresponding to a short pulse width of the first clock signal SS.
摘要翻译：本发明的目的是提供一种能够以低功耗改变时钟周期的定时电路。定时电路包括时钟发生器11，比较器12和13，用于分别比较输入的控制电压TDV和参考电压VR，分别用于保持比较器的输出的保持电路18和19以及用于产生电路的电路20,21和22 定时脉冲TDT作为其输出，基于保持电路的输出和从时钟发生器输出的时钟信号。每个比较器接收从时钟发生器输出的第一时钟信号SS，并且仅对与第一时钟信号SS的短脉冲宽度相对应的时间进行操作。

10. 发明授权

US07460538B2 Communication control apparatus and method for searching an internet protocol address 失效
标题翻译：用于搜索因特网协议地址的通信控制装置和方法
公开(公告)号：US07460538B2
公开(公告)日：2008-12-02
申请号：US10780213
申请日：2004-02-17
申请人： Yoshihisa Takatsu , Shinpei Watanabe , Masaya Mori , Toshio Sunaga
发明人： Yoshihisa Takatsu , Shinpei Watanabe , Masaya Mori , Toshio Sunaga
IPC分类号： H04L12/28 , H04J1/16 , G08C15/00 , G06F11/00
CPC分类号： H04L45/00 , H04L45/48 , H04L45/7457 , Y10S707/99935
摘要： A communication control apparatus includes search information associated with a tree structure. A mask prefix is associated with at least one entry, each entry including information on the mask length of a mask prefix associated therewith and a sort key. Each entry is assigned to a node in the tree structure according to a sorting order. Each node is linked to a different node at the next lower hierarchy via a branch based on the entry of the node. A destination address of the packet received is first extracted, and a search target node specified by a search control for an entry having information on the best matched prefix of the extracted address is then searched for. After completion of the node-by-node search process, a transfer route is determined for the packet received based on the longest prefix amongst the most appropriate prefixes of all the current search target nodes.
摘要翻译：通信控制装置包括与树结构相关联的搜索信息。掩码前缀与至少一个条目相关联，每个条目包括与其相关联的掩码前缀的掩码长度和排序密钥的信息。每个条目根据排序顺序分配给树结构中的一个节点。每个节点通过基于节点的条目的分支链接到下一个较低层次上的不同节点。首先提取接收到的分组的目的地地址，然后搜索由具有关于提取的地址的最佳匹配前缀的信息的条目的搜索控制指定的搜索目标节点。在逐节点搜索处理完成之后，基于所有当前搜索目标节点的最适合的前缀中的最长前缀来确定接收的分组的传输路由。

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