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1. 发明授权

US06162344A Method of electroplating semiconductor wafer using variable currents and mass transfer to obtain uniform plated layer 有权
标题翻译：使用可变电流和质量传递电镀半导体晶片以获得均匀的镀层的方法
公开(公告)号：US06162344A
公开(公告)日：2000-12-19
申请号：US393226
申请日：1999-09-09
申请人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
发明人： Jonathan D. Reid , Robert J. Contolini , Edward C. Opocensky , Evan E. Patton , Eliot K. Broadbent
IPC分类号： C25D5/18 , C25D7/12 , C25D5/00
CPC分类号： C25D5/18 , C25D7/123 , Y10S205/915
摘要： In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region. As a result, the portion of the layer formed under these conditions is thinner near the edge of the wafer.
摘要翻译：在电镀半导体晶片上的金属层时，电极端子所在的晶片边缘与晶片的中心之间的电阻电压降使得电镀速率在边缘比在中心处更大。作为这种所谓的“终端效应”的结果，镀层倾向于是凹的。通过首先将电流设置在相对低的电平直到电镀层足够厚以使电阻降可忽略，然后增加电流以提高电镀速率来克服该问题。或者，可以使在较高电流下产生的层的部分略微凸起，以补偿在较低电流下产生的层的部分的凹形。这是通过减少靠近晶片边缘的电镀溶液的质量传递来实现的，即在该区域中电镀过程被传质限制。结果，在这些条件下形成的层的部分在晶片的边缘附近更薄。

2. 发明授权

US06716334B1 Electroplating process chamber and method with pre-wetting and rinsing capability 有权
标题翻译：电镀工艺室和预润湿和冲洗能力的方法
公开(公告)号：US06716334B1
公开(公告)日：2004-04-06
申请号：US09829848
申请日：2001-04-09
申请人： Jonathan D. Reid , Steven W. Taatjes , Robert J. Contolini , Evan E. Patton
发明人： Jonathan D. Reid , Steven W. Taatjes , Robert J. Contolini , Evan E. Patton
IPC分类号： C25D502
CPC分类号： H01L21/67034 , C25D7/123 , C25D17/001 , C25D17/06 , C25D21/00 , C25D21/08 , C25D21/18
摘要： A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
摘要翻译：电镀槽具有内浸镀液容器，用于在浸没在由内镀浴容器所包含的溶液中的工件（例如，晶片）上进行电镀。回收入口将任何溢出内部镀浴容器的溶液漏回到储存容器中，以循环回内部镀浴容器。还提供废物通道，其具有与回收通道的入口不同的高度的入口。电镀后，将晶片提升到一个位置并旋转。在旋转的同时，将晶片用例如超纯水彻底冲洗。晶圆的旋转速度和高度决定了水和溶液是通过回收通道还是通过废物通道进行回收。

3. 发明授权

US06569299B1 Membrane partition system for plating of wafers 有权
标题翻译：用于电镀晶片的隔膜系统
公开(公告)号：US06569299B1
公开(公告)日：2003-05-27
申请号：US09574666
申请日：2000-05-18
申请人： Jonathan David Reid , Robert J. Contolini , John Owen Dukovic
发明人： Jonathan David Reid , Robert J. Contolini , John Owen Dukovic
IPC分类号： C25B1300
CPC分类号： C25D17/10 , C25D17/00 , C25D17/001 , C25D17/008
摘要： An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.
摘要翻译：阳极包括阳极杯，膜和离子源材料，阳极杯和膜形成离子源材料所在的外壳。阳极杯包括具有中心孔的基部，并且膜还具有中心孔。射流穿过阳极杯的基部的中心孔并通过膜，允许电镀溶液指向正在电镀的晶片的中心。

4. 发明授权

US06214193B1 Electroplating process including pre-wetting and rinsing 有权
标题翻译：电镀工艺包括预润湿和冲洗
公开(公告)号：US06214193B1
公开(公告)日：2001-04-10
申请号：US09374253
申请日：1999-08-13
申请人： Jonathan D. Reid , Steven W. Taatjes , Robert J. Contolini , Evan E. Patton
发明人： Jonathan D. Reid , Steven W. Taatjes , Robert J. Contolini , Evan E. Patton
IPC分类号： C25D502
CPC分类号： H01L21/67034 , C25D7/123 , C25D17/06 , C25D21/00 , C25D21/08 , C25D21/18 , C25D21/20
摘要： A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.
摘要翻译：电镀槽具有内浸镀液容器，用于在浸没在由内镀浴容器所包含的溶液中的工件（例如，晶片）上进行电镀。回收入口将任何溢出内部镀浴容器的溶液漏回到储存容器中，以循环回内部镀浴容器。还提供废物通道，其具有与回收通道的入口不同的高度的入口。电镀后，将晶片提升到一个位置并旋转。在旋转的同时，将晶片用例如超纯水彻底冲洗。晶圆的旋转速度和高度决定了水和溶液是通过回收通道还是通过废物通道进行回收。

5. 发明授权

US06193870B1 Use of a hard mask for formation of gate and dielectric via nanofilament field emission devices 失效
标题翻译：使用硬掩模通过纳米丝场发射器件形成栅极和电介质
公开(公告)号：US06193870B1
公开(公告)日：2001-02-27
申请号：US08847085
申请日：1997-05-01
申请人： Jeffrey D. Morse , Robert J. Contolini
发明人： Jeffrey D. Morse , Robert J. Contolini
IPC分类号： C25D502
CPC分类号： H01J9/025 , C25D1/04 , H01L21/0332 , H01L21/31116 , H01L21/31144
摘要： A process for fabricating a nanofilament field emission device in which a via in a dielectric layer is self-aligned to gate metal via structure located on top of the dielectric layer. By the use of a hard mask layer located on top of the gate metal layer, inert to the etch chemistry for the gate metal layer, and in which a via is formed by the pattern from etched nuclear tracks in a trackable material, a via is formed by the hard mask will eliminate any erosion of the gate metal layer during the dielectric via etch. Also, the hard mask layer will protect the gate metal layer while the gate structure is etched back from the edge of the dielectric via, if such is desired. This method provides more tolerance for the electroplating of a nanofilament in the dielectric via and sharpening of the nanofilament.
摘要翻译：一种制造纳米丝场发射器件的方法，其中电介质层中的通孔与位于介电层顶部的栅极金属通孔结构自对准。通过使用位于栅极金属层顶部的硬掩模层，对栅极金属层的蚀刻化学物质是惰性的，并且其中通过可追踪材料中蚀刻的核磁道的图案形成通孔，通孔是由硬掩模形成将消除电介质通孔蚀刻期间栅极金属层的任何侵蚀。此外，如果需要的话，硬掩模层将保护栅极金属层，同时栅极结构从电介质通孔的边缘被回蚀。该方法提供了对纳米丝在电介质通孔中的电镀和纳米丝的锐化的更大的公差。

6. 发明授权

US6159354A Electric potential shaping method for electroplating 失效
标题翻译：电镀电位成形方法
公开(公告)号：US6159354A
公开(公告)日：2000-12-12
申请号：US970120
申请日：1997-11-13
申请人： Robert J. Contolini , Jonathan Reid , Evan Patton , Jingbin Feng , Steve Taatjes , John Owen Dukovic
发明人： Robert J. Contolini , Jonathan Reid , Evan Patton , Jingbin Feng , Steve Taatjes , John Owen Dukovic
IPC分类号： C25D7/12 , C25D5/00 , C25D3/38 , C25D5/20 , C25D7/04
CPC分类号： C25D7/12 , C25D17/001
摘要： An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
摘要翻译：用于在晶片表面上沉积导电层的设备包括凸缘。凸缘具有圆柱形壁和连接到圆柱形壁的第一端的环形空间。在电镀过程中，环形屏蔽了晶片表面的边缘区域，从而减小了边缘区域上沉积的导电层的厚度。此外，凸缘的圆柱形壁可以设置有与晶片相邻的多个孔，允许夹在晶片表面上的气泡容易地逸出。

7. 发明授权

US6045678A Formation of nanofilament field emission devices 失效
标题翻译：纳米丝场发射装置的形成
公开(公告)号：US6045678A
公开(公告)日：2000-04-04
申请号：US847088
申请日：1997-05-01
申请人： Jeffrey D. Morse , Robert J. Contolini , Ronald G. Musket , Anthony F. Bernhardt
发明人： Jeffrey D. Morse , Robert J. Contolini , Ronald G. Musket , Anthony F. Bernhardt
IPC分类号： C25D7/12 , C25D5/02
CPC分类号： C25D7/12
摘要： A process for fabricating a nanofilament field emission device. The process enables the formation of high aspect ratio, electroplated nanofilament structure devices for field emission displays wherein a via is formed in a dielectric layer and is self-aligned to a via in the gate metal structure on top of the dielectric layer. The desired diameter of the via in the dielectric layer is on the order of 50-200 nm, with an aspect ratio of 5-10. In one embodiment, after forming the via in the dielectric layer, the gate metal is passivated, after which a plating enhancement layer is deposited in the bottom of the via, where necessary. The nanofilament is then electroplated in the via, followed by removal of the gate passification layer, etch back of the dielectric, and sharpening of the nanofilament. A hard mask layer may be deposited on top of the gate metal and removed following electroplating of the nanofilament.
摘要翻译：一种制造纳米丝场发射器件的方法。该方法能够形成高纵横比，用于场致发射显示器的电镀纳米丝结构器件，其中通孔形成在电介质层中，并且与电介质层顶部的栅极金属结构中的通孔自对准。电介质层中通孔的理想直径约为50-200nm，纵横比为5-10。在一个实施例中，在电介质层中形成通孔之后，栅极金属被钝化，之后必要时在通孔的底部沉积电镀增强层。然后将纳米丝电镀在通孔中，随后除去栅极钝化层，回蚀电介质，并使纳米丝的锐化。硬掩模层可以沉积在栅极金属的顶部上，并在纳米丝的电镀之后去除。

8. 发明授权

US06709565B2 Method and apparatus for uniform electropolishing of damascene ic structures by selective agitation 有权
标题翻译：通过选择性搅拌均匀电解抛光镶嵌结构的方法和装置
公开(公告)号：US06709565B2
公开(公告)日：2004-03-23
申请号：US09967075
申请日：2001-09-28
申请人： Steven T. Mayer , Robert J. Contolini , Eliot K. Broadbent , John S. Drewery
发明人： Steven T. Mayer , Robert J. Contolini , Eliot K. Broadbent , John S. Drewery
IPC分类号： B23H1100
CPC分类号： B23H5/08 , H01L21/32115 , H01L21/3212 , H01L21/32134
摘要： The present invention pertains to apparatus and methods for planarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by increasing the fluid agitation in raised regions with respect to recessed regions. That is, the agitation of the electropolishing bath fluid is agitated or exchanged as a function of elevation on the metal film profile. The higher the elevation, the greater the movement or exchange rate of bath fluid. In preferred methods of the invention, this agitation is achieved through the use of a microporous electropolishing pad that moves over (either near or in contact with) the surface of the wafer during the electropolishing process. Thus, methods of the invention are electropolishing methods, which in some cases include mechanical polishing elements.
摘要翻译：本发明涉及在大范围的特征尺寸上具有凹陷和凸起特征的金属表面的平坦化的装置和方法。本发明通过增加相对于凹陷区域的凸起区域中的流体搅拌来实现。也就是说，作为金属膜轮廓上的仰角的函数来搅动或更换电抛光浴液的搅动。海拔越高，浴液的运动或汇率越高。在本发明的优选方法中，通过使用在电解抛光过程中在晶片表面上移动（接近或接触）的微孔电解抛光垫来实现该搅拌。因此，本发明的方法是电抛光方法，其在一些情况下包括机械抛光元件。

9. 发明授权

US06514393B1 Adjustable flange for plating and electropolishing thickness profile control 失效
标题翻译：可调法兰电镀和电解抛光厚度剖面控制
公开(公告)号：US06514393B1
公开(公告)日：2003-02-04
申请号：US09542890
申请日：2000-04-04
申请人： Robert J. Contolini , Andrew J. McCutcheon
发明人： Robert J. Contolini , Andrew J. McCutcheon
IPC分类号： C25C1704
CPC分类号： C25D7/12 , C25D7/123 , C25D17/001 , C25D17/06
摘要： An electrochemical reactor is used to electrofill damascene architecture for integrated circuits or for electropolishing magnetic disks. An inflatable bladder is used to screen the applied field during electroplating operations to compensate for potential drop along the radius of a wafer. The bladder establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film seed layer of copper on the wafer.
摘要翻译：电化学反应器用于对集成电路或电解抛光磁盘的大马士革结构进行电解填充。在电镀操作期间使用可膨胀的气囊来屏蔽所施加的磁场，以补偿沿着晶片半径的电位降。膀胱在电解液中产生反向电位降，以克服晶片上的铜薄膜晶种层的电阻。

10. 发明授权

US06193859B1 Electric potential shaping apparatus for holding a semiconductor wafer during electroplating 失效
标题翻译：电镀期间保持半导体晶片的电位成形装置
公开(公告)号：US06193859B1
公开(公告)日：2001-02-27
申请号：US09074624
申请日：1998-05-07
申请人： Robert J. Contolini , Jonathan Reid , Evan Patton , Jingbin Feng , Steve Taatjes , John Owen Dukovic
发明人： Robert J. Contolini , Jonathan Reid , Evan Patton , Jingbin Feng , Steve Taatjes , John Owen Dukovic
IPC分类号： C25D1700
CPC分类号： C25D7/12 , C25D17/001
摘要： An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
摘要翻译：用于在晶片表面上沉积导电层的设备包括凸缘。凸缘具有圆柱形壁和连接到圆柱形壁的第一端的环形空间。在电镀过程中，环形屏蔽了晶片表面的边缘区域，从而减小了边缘区域上沉积的导电层的厚度。此外，凸缘的圆柱形壁可以设置有与晶片相邻的多个孔，允许夹在晶片表面上的气泡容易地逸出。

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