专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06362644B1 Programmable termination for integrated circuits 有权
标题翻译：集成电路的可编程终端
公开(公告)号：US06362644B1
公开(公告)日：2002-03-26
申请号：US09630090
申请日：2000-08-01
申请人： Philip A. Jeffery , Stephen G. Shook
发明人： Philip A. Jeffery , Stephen G. Shook
IPC分类号： H03K1716
CPC分类号： H03K19/01837
摘要： A receiver circuit (16) is programmable to operate with different logic family driver circuits (10). The receiver circuit has two external configuration pins (22,) 24) that are configured to provide the necessary termination for the type of logic family driver circuit used. To terminate the receiver circuit (16) for an ECL application will require first and second configuration pins (22,24) are connected to VCC—2 volts. To terminate the receiver circuit (16) for a CML application will require the first configuration pin (22) and the second configuration pin (24) are connected to VCC. LVDS termination for the receiver circuit (16) requires the first configuration pin (22) and the second configuration pin (24) are connected together. The configuration pins are external to a semiconductor package (14) housing the receiver circuit.
摘要翻译：接收器电路（16）可编程为与不同的逻辑系列驱动电路（10）一起工作。接收器电路具有两个外部配置引脚（22），其被配置为为所使用的逻辑系列驱动器电路的类型提供必要的端接。为了终止用于ECL应用的接收机电路（16），将需要将第一和第二配置引脚（22,24）连接到VCC-2伏特。为了终止用于CML应用的接收机电路（16）将需要第一配置引脚（22）和第二配置引脚（24）连接到VCC。接收器电路（16）的LVDS终端需要第一配置引脚（22）和第二配置引脚（24）连接在一起。配置引脚位于容纳接收器电路的半导体封装（14）的外部。

2. 发明授权

US06411129B1 Logic circuit with output high voltage boost and method of using 有权
标题翻译：输出高电压升压逻辑电路及使用方法
公开(公告)号：US06411129B1
公开(公告)日：2002-06-25
申请号：US09677610
申请日：2000-10-03
申请人： Philip A. Jeffery
发明人： Philip A. Jeffery
IPC分类号： H03K1920
CPC分类号： H03K19/086 , H03K19/0136
摘要： A differential logic gate providing complimentary input and complimentary output operation. Transistors (50,52) provide the differential input and emitter follower transistors (54,62) provide the complimentary outputs. Enhanced output high logic levels are enabled by PNP transistors (40,46). PNP transistors (40,46) supply base current drive to transistors (54,62) which boosts the output logic high voltage values presented at terminals (Q,Q-compliment) by reducing collector resistor voltage drop across resistors (42,44). PNP transistors (40,46) remain in their respective conductive states due to voltage regulators (38,48) to provide for faster operation.
摘要翻译：差分逻辑门提供免费输入和互补输出操作。晶体管（50,52）提供差分输入和射极跟随器晶体管（54,62）提供互补输出。增强的输出高逻辑电平由PNP晶体管（40,46）使能。 PNP晶体管（40,46）向晶体管（54,62）提供基极电流驱动，通过减少电阻器（42,44）上的集电极电阻器电压降，从而提高端子（Q，Q-补码）上提供的输出逻辑高电压值。 PNP晶体管（40,46）由于电压调节器（38,48）而保持在它们各自的导通状态，以提供更快的操作。

3. 发明授权

US4486880A Output multiplexer having one gate delay 失效
标题翻译：输出多路复用器具有一个门延迟
公开(公告)号：US4486880A
公开(公告)日：1984-12-04
申请号：US447928
申请日：1982-12-09
申请人： Philip A. Jeffery , L. J. Reed , Harold L. Spangler
发明人： Philip A. Jeffery , L. J. Reed , Harold L. Spangler
IPC分类号： H04J3/04 , H03K17/00 , H03K17/62 , H04J15/00
CPC分类号： H03K17/005 , H03K17/6264
摘要： A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.
摘要翻译：多路复用器包括具有响应于数字选择信号的多个OR门的选择电路。 OR门内的晶体管是集电极点，并且向多个AND门提供多个选择电路输出，其也响应于多个输入信号。选择电路的四个OR门的集电极点提供具有数据传输的单个门延迟的多路复用器。多路复用器通过仅为AND门单个电流源消耗较少的电流。

4. 发明授权

US5818890A Method for synchronizing signals and structures therefor 失效
标题翻译：用于同步信号和结构的方法
公开(公告)号：US5818890A
公开(公告)日：1998-10-06
申请号：US719423
申请日：1996-09-24
申请人： David K. Ford , Philip A. Jeffery , Phuc C. Pham
发明人： David K. Ford , Philip A. Jeffery , Phuc C. Pham
IPC分类号： G06F13/42 , H04L7/027 , H04L7/033 , H03D3/24
CPC分类号： H04L7/0338
摘要： A serial data signal is synchronized to a clock signal in a synchronization circuit (10). Synchronization is accomplished by generating a plurality of delayed versions of the serial data signal using serially connected delay elements (21-27). The delayed versions of the serial data signal are sampled using a set of flip-flops (11-18). The sampled delayed data signals appearing at the outputs of each flip-flop of the set of flip-flops (11-18) are used to determine which delayed data signal is most closely aligned to the clock signal. The output of the multiplexer (40) is an aligned serial data signal. In addition, a drift correction circuit (50) continuously monitors and corrects the alignment between the clock signal and the aligned serial data signal.
摘要翻译：串行数据信号与同步电路（10）中的时钟信号同步。通过使用串行连接的延迟元件（21-27）生成串行数据信号的多个延迟版本来实现同步。使用一组触发器（11-18）对串行数据信号的延迟版本进行采样。出现在触发器组（11-18）的每个触发器的输出处的采样的延迟数据信号用于确定哪个延迟的数据信号与时钟信号最紧密地对准。多路复用器（40）的输出是对准的串行数据信号。此外，漂移校正电路（50）连续地监视和校正时钟信号和对准的串行数据信号之间的对准。

5. 发明授权

US5023479A Low power output gate 失效
标题翻译：低功率输出门
公开(公告)号：US5023479A
公开(公告)日：1991-06-11
申请号：US560920
申请日：1990-07-31
申请人： Philip A. Jeffery , Bor-Yuan Hwang
发明人： Philip A. Jeffery , Bor-Yuan Hwang
IPC分类号： H03K19/08 , H03K19/00 , H03K19/086 , H03K19/0944
CPC分类号： H03K19/001 , H03K19/09448
摘要： A low power BiMOS output gate includes an input circuit for passing current through its first and second outputs in response to logic states occurring on first and second input signals which are respectively applied at first and second inputs of the input circuit. A field-effect transistor has first and second electrodes and a control electrode, the control electrode is coupled to the first output of the input circuit, the first electrode is coupled to the second output of the input circuit, and the second electrode is coupled to a first supply voltage terminal. A first resistor is coupled across the second and control electrodes of the field-effect transistor while a second resistor is coupled across the first and second electrodes of the field-effect transistor such that when the first input signal is in a first logic state, the voltage drop occurring across the first resistor will render the field-effect transistor operative wherein the effective resistance of the second resistor is decreased. Also, an output circuit is coupled to the second output of the input circuit for providing an output logic signal at an output terminal of the BiMOS output gate.
摘要翻译：低功率BiMOS输出门包括输入电路，用于响应于分别在输入电路的第一和第二输入端施加的第一和第二输入信号上发生的逻辑状态而使电流通过其第一和第二输出。场效应晶体管具有第一和第二电极和控制电极，控制电极耦合到输入电路的第一输出，第一电极耦合到输入电路的第二输出，第二电极耦合到第一电源电压端子。第一电阻器耦合在场效应晶体管的第二和控制电极之间，而第二电阻器耦合在场效应晶体管的第一和第二电极两端，使得当第一输入信号处于第一逻辑状态时，在第一电阻器两端发生的电压降将导致场效应晶体管工作，其中第二电阻器的有效电阻降低。此外，输出电路耦合到输入电路的第二输出端，用于在BiMOS输出门的输出端提供输出逻辑信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式