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1. 发明授权

US4486880A Output multiplexer having one gate delay 失效
标题翻译：输出多路复用器具有一个门延迟
公开(公告)号：US4486880A
公开(公告)日：1984-12-04
申请号：US447928
申请日：1982-12-09
申请人： Philip A. Jeffery , L. J. Reed , Harold L. Spangler
发明人： Philip A. Jeffery , L. J. Reed , Harold L. Spangler
IPC分类号： H04J3/04 , H03K17/00 , H03K17/62 , H04J15/00
CPC分类号： H03K17/005 , H03K17/6264
摘要： A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.
摘要翻译：多路复用器包括具有响应于数字选择信号的多个OR门的选择电路。 OR门内的晶体管是集电极点，并且向多个AND门提供多个选择电路输出，其也响应于多个输入信号。选择电路的四个OR门的集电极点提供具有数据传输的单个门延迟的多路复用器。多路复用器通过仅为AND门单个电流源消耗较少的电流。

2. 发明授权

US4980579A ECL gate having dummy load for substantially reducing skew 失效
标题翻译： ECL门具有用于显着减少偏斜的虚拟负载
公开(公告)号：US4980579A
公开(公告)日：1990-12-25
申请号：US237370
申请日：1988-08-29
申请人： James T. McDonald , Rajnish Maini , Harold L. Spangler
发明人： James T. McDonald , Rajnish Maini , Harold L. Spangler
IPC分类号： H03K19/003 , H03K19/082 , H03K19/086
CPC分类号： H03K19/086 , H03K19/00323 , H03K19/0826
摘要： An active dummy load substantially reduces skews for input signals of a CML or an ECL series gate by generating a selectable capacitance that adjusts the delay time of the output signal in relation to the changing of the input signal to one of two states.
摘要翻译：有源虚拟负载通过产生可选择的电容来大大减少CML或ECL系列门的输入信号的偏差，该可选择的电容将输出信号的延迟时间相对于输入信号的变化调整到两种状态之一。

3. 发明授权

US5130674A Voltage controlled oscilator having controlled bias voltage, AGC and output amplifier 失效
标题翻译：具有受控偏压的压控式振荡器，AGC和输出放大器
公开(公告)号：US5130674A
公开(公告)日：1992-07-14
申请号：US767951
申请日：1991-09-30
申请人： Phuc C. Pham , Gregory A. Davis , Harold L. Spangler
发明人： Phuc C. Pham , Gregory A. Davis , Harold L. Spangler
IPC分类号： H03B5/12
CPC分类号： H03B5/1231 , H03B5/1203 , H03B5/1243 , H03B2200/0034
摘要： A voltage controlled oscillator circuit including an oscillator circuit having first and second terminals to which an external inductance is connected. A frequency control voltage (V.sub.F) is applied through a bias circuit to the second terminal for varying the center frequency. The oscillator circuit may have an AGC circuit or a modulation circuit connected to it. An output amplifier is connected with the first terminal and has an adjustable output impedance for matching the input impedance of a load circuit.
摘要翻译：一种压控振荡器电路，包括具有连接外部电感的第一和第二端子的振荡器电路。频率控制电压（VF）通过偏置电路施加到第二端子以改变中心频率。振荡器电路可以具有与之相连的AGC电路或调制电路。输出放大器与第一端子连接，具有可调整的输出阻抗，用于匹配负载电路的输入阻抗。

4. 发明授权

US4926066A Clock distribution circuit having minimal skew 失效
标题翻译：时钟分配电路具有最小的偏移
公开(公告)号：US4926066A
公开(公告)日：1990-05-15
申请号：US242666
申请日：1988-09-12
申请人： Rajnish Maini , Harold L. Spangler
发明人： Rajnish Maini , Harold L. Spangler
IPC分类号： H01L27/02
CPC分类号： H01L27/0207 , H01L24/06 , H01L2924/14
摘要： A clock distribution circuit for distributing a clock signal to a plurality of other circuits, having a substantially reduced skew between the input signal and the plurality of output signals wherein signals are transmitted from an input gate to a plurality of output gates and output pads along radially disposed metalization lines. The radially disposed metalization lines are terminated at forty five degrees, thereby reducing reflections, and are of equal length for like signals.
摘要翻译：一种时钟分配电路，用于将时钟信号分配给多个其它电路，其具有在输入信号和多个输出信号之间大幅减小的偏差，其中信号从输入门传输到多个输出门，并沿着径向输出输出衬垫处理金属化生产线。径向设置的金属化线以四十五度终止，从而减少反射，并且对于类似的信号具有相同的长度。

5. 发明授权

US4942358A Integrated circuit option identification circuit and method 失效
标题翻译：集成电路选择识别电路及方法
公开(公告)号：US4942358A
公开(公告)日：1990-07-17
申请号：US266446
申请日：1988-11-02
申请人： Gregory A. Davis , Harold L. Spangler
发明人： Gregory A. Davis , Harold L. Spangler
IPC分类号： G06F11/00 , H01L23/544
CPC分类号： H01L23/544 , G06F11/006 , H01L2223/5444 , H01L2223/54473 , H01L2924/0002
摘要： An identification circuit for use in identifying at least two integrated circuits having the same logic function but different input/output characteristics, each circuit having first and second isolated power supply conductors. A unilateral current conducting circuit having an input and an output is coupled between the first and second power supply conductors via conductive jumpers in all but one of the identifiable integrated circuits. The conductive jumpers are removed for one integrated circuit family. The other integrated circuit families have unique combinations of a resistor and at least one serially coupled diode wherein a predetermined potential is required to induce current to flow therethrough for each family. The potential of the first power supply conductor is increased in predetermined steps until current flow is detected, or a predetermined maximum potential is reached. The combination of the presence or absence of current flow and the potential at the first power supply conductor associated therewith provide the identification of the integrated circuit.
摘要翻译：一种用于识别具有相同逻辑功能但具有不同输入/输出特性的至少两个集成电路的识别电路，每个电路具有第一和第二隔离电源导体。具有输入和输出的单向电流传导电路经由所有可识别的集成电路中的所有集成电路中的所有导电跳线耦合在第一和第二电源导体之间。为一个集成电路系列移除导电跳线。其他集成电路系列具有电阻器和至少一个串联耦合二极管的独特组合，其中需要预定电位以诱导电流流过每个系列。第一电源导体的电位以预定步骤增加，直到检测到电流流动或达到预定的最大电位。电流的存在或不存在以及与其相关联的第一电源导体处的电位的组合提供了集成电路的识别。

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