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1. 发明授权

US07164175B2 Semiconductor device with silicon-film fins and method of manufacturing the same 失效
标题翻译：具有硅膜翅片的半导体器件及其制造方法
公开(公告)号：US07164175B2
公开(公告)日：2007-01-16
申请号：US10835122
申请日：2004-04-28
申请人： Hirohisa Kawasaki , Kazunari Ishimaru
发明人： Hirohisa Kawasaki , Kazunari Ishimaru
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0207 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/66795
摘要： A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
摘要翻译：半导体器件包括半导体衬底，投影在半导体衬底的表面上的绝缘膜，设置在绝缘膜的侧表面上的半导体膜和形成在半导体膜中的MIS晶体管，所述MIS晶体管具有源极，栅极和漏区。半导体器件还包括设置在MIS晶体管的栅极区上的栅电极，栅电极的长度大于半导体膜的厚度。

2. 发明申请

US20060278903A1 Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same 失效
标题翻译：在半导体层中具有电致伸缩层的半导体器件及其制造方法
公开(公告)号：US20060278903A1
公开(公告)日：2006-12-14
申请号：US11443430
申请日：2006-05-31
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L29/76 , H01L29/94 , H01L27/108 , H01L31/00 , H01L31/119
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/78 , H01L29/7846
摘要： A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.
摘要翻译：半导体器件包括第一半导体层和设置在第一半导体层的主表面区域中的第一导电类型的第一绝缘栅场效应晶体管。所述半导体器件还包括电致伸缩层，所述电致伸缩层设置在所述第一半导体层的背表面上，并且当所述第一绝缘栅极场中的所述第一绝缘栅场时，沿着沟道长度施加第一应力至所述第一绝缘栅场效应晶体管的沟道区效果晶体管工作。

3. 发明申请

US20060275988A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060275988A1
公开(公告)日：2006-12-07
申请号：US11404772
申请日：2006-04-17
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

4. 发明申请

US20060237788A1 Semiconductor device and its fabrication method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060237788A1
公开(公告)日：2006-10-26
申请号：US11364552
申请日：2006-03-01
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823443 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of the first gate electrode and made of a material having dielectric constant smaller than that of the first gate insulating film, and a second MOSFET which has a second gate insulating film made of a material having dielectric constant smaller than that of the first gate insulating film formed above the semiconductor substrate and a second gate electrode formed above the second gate insulating film, wherein the first gate electrode is formed of a first silicide or a first metal; and the second gate electrode is formed including a film made of at least one of polysilicon, amorphous silicon, polysilicon germanium and amorphous silicon germanium.
摘要翻译：半导体器件具有半导体衬底，第一MOSFET，其具有由半导体衬底上形成的高电介质材料制成的第一栅极绝缘膜和形成在第一栅极绝缘膜上方的第一栅电极，直接形成在绝缘膜上的绝缘膜所述第一栅电极的侧壁由介电常数小于所述第一栅极绝缘膜的介电常数的材料制成;以及第二MOSFET，其具有由介电常数小于所述第一栅极绝缘膜的介电常数的材料制成的第二栅极绝缘膜形成在所述半导体衬底上方的膜和形成在所述第二栅极绝缘膜上方的第二栅电极，其中所述第一栅电极由第一硅化物或第一金属形成; 并且形成第二栅电极，其包括由多晶硅，非晶硅，多晶硅锗和非晶硅锗中的至少一种制成的膜。

5. 发明授权

US5886387A BiCMOS semiconductor integrated circuit device having MOS transistor and bipolar transistor regions of different thickness 失效
标题翻译：具有MOS晶体管的BiCMOS半导体集成电路器件和不同厚度的双极晶体管区域
公开(公告)号：US5886387A
公开(公告)日：1999-03-23
申请号：US716729
申请日：1996-09-23
申请人： Masahito Nishigohri , Kazunari Ishimaru
发明人： Masahito Nishigohri , Kazunari Ishimaru
IPC分类号： H01L27/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/0623
摘要： Disclosed are a semiconductor integrated circuit device capable of including both a bipolar transistor and a MOS transistor while maintaining high performances of then both and a method of fabricating the device. On a p-type silicon substrate a plurality of n.sup.+ -type regions are formed below the buried collector region of a bipolar transistor and the n-type well region of a MOS transistor. A plurality of p-type regions are formed below the isolation region of the bipolar transistor and the p-type well region of the MOS transistor. An epitaxial layer is formed on the substrate including these n.sup.+ -type and p-type regions. This epitaxial layer forms element region layers having a bipolar transistor region and a MOS transistor region. The thickness of the layer of the bipolar transistor region is smaller than that of the layer of the MOS transistor region.
摘要翻译：公开了一种半导体集成电路器件，其能够包括双极晶体管和MOS晶体管，同时保持两者的高性能，以及制造该器件的方法。在p型硅衬底上，在双极晶体管的掩埋集电极区域和MOS晶体管的n型阱区域的下方形成多个n +型区域。在双极晶体管的隔离区域和MOS晶体管的p型阱区域的下方形成多个p型区域。在包括这些n +型和p型区的衬底上形成外延层。该外延层形成具有双极晶体管区域和MOS晶体管区域的元件区域层。双极晶体管区域的层的厚度小于MOS晶体管区域的厚度。

6. 发明授权

US07541245B2 Semiconductor device with silicon-film fins and method of manufacturing the same 有权
标题翻译：具有硅膜翅片的半导体器件及其制造方法
公开(公告)号：US07541245B2
公开(公告)日：2009-06-02
申请号：US11637734
申请日：2006-12-12
申请人： Hirohisa Kawasaki , Kazunari Ishimaru
发明人： Hirohisa Kawasaki , Kazunari Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0207 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/66795
摘要： A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
摘要翻译：半导体器件包括半导体衬底，投影在半导体衬底的表面上的绝缘膜，设置在绝缘膜的侧表面上的半导体膜和形成在半导体膜中的MIS晶体管，所述MIS晶体管具有源极，栅极和漏区。半导体器件还包括设置在MIS晶体管的栅极区上的栅电极，栅电极的长度大于半导体膜的厚度。

7. 发明授权

US07468923B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07468923B2
公开(公告)日：2008-12-23
申请号：US11613460
申请日：2006-12-20
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/02 , G11C7/1078 , G11C7/1087
摘要： There is provided a semiconductor integrated circuit including a logic circuit and a writing circuit configured to receive a writing data outputted from the logic circuit, invert the writing data to generate an inverted data, compare the writing data with the inverted data and output the held writing data if the writing data is different from the inverted data.
摘要翻译：提供了一种包括逻辑电路和写入电路的半导体集成电路，其被配置为接收从逻辑电路输出的写入数据，反转写入数据以产生反相数据，将写入数据与反相数据进行比较，并输出保持的写入数据如果写入数据与反转数据不同。

8. 发明授权

US07235469B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07235469B2
公开(公告)日：2007-06-26
申请号：US10998193
申请日：2004-11-29
申请人： Yasunori Okayama , Kiyotaka Miyano , Kazunari Ishimaru
发明人： Yasunori Okayama , Kiyotaka Miyano , Kazunari Ishimaru
IPC分类号： H01L21/26
CPC分类号： H01L29/4232 , H01L21/823835 , H01L21/823842 , H01L29/665
摘要： A semiconductor device suitable for the miniaturization and comprising properly controlled Si/SiGe gate electrode comprises an insulator formed on a semiconductor substrate, a first gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is higher near an interface to the insulator and lower in a surface side opposite to the insulator, and a second gate electrode formed on the insulator and including silicon-germanium, wherein a germanium concentration is substantially uniform and an n-type dopant of a concentration of above 6×1020 atoms/cm3 is contained.
摘要翻译：适用于小型化并且包括适当控制的Si / SiGe栅电极的半导体器件包括形成在半导体衬底上的绝缘体，形成在绝缘体上并包括硅 - 锗的第一栅电极，其中锗浓度在与绝缘体，并且在与绝缘体相对的表面侧下方，以及形成在绝缘体上并包括硅锗的第二栅电极，其中锗浓度基本上均匀，并且浓度高于6×10 20的n型掺杂剂原子/ cm 3含有。

9. 发明授权

US07061054B2 Semiconductor device and semiconductor device manufacturing method 失效
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US07061054B2
公开(公告)日：2006-06-13
申请号：US10680101
申请日：2003-10-08
申请人： Kanna Tomiye , Akira Hokazono , Kazunari Ishimaru
发明人： Kanna Tomiye , Akira Hokazono , Kazunari Ishimaru
IPC分类号： H01L29/786
CPC分类号： H01L27/105 , H01L21/84 , H01L27/11 , H01L27/1116 , H01L27/1203 , H01L29/785 , Y10S257/903
摘要： A semiconductor device has a first and a second semiconductor layer provided on an insulating film on a support substrate. A first memory cell transistor, which constitutes a part of a memory cell in an SRAM, has a first gate electrode of a first conductivity type and first source/drain diffusion layers of a second conductivity type opposite to the first conductivity type. The following expression is fulfilled the thickness of the first conductivity type≦one-third of a length of the first gate electrode in its channel length. A first peripheral transistor, which constitutes a part of a peripheral circuit, has a third gate electrode and a third source/drain diffusion layers. The following expression is satisfied the thickness of the second semiconductor layer>one-third of a length of the third gate electrode in its channel length direction.
摘要翻译：半导体器件具有设置在支撑衬底上的绝缘膜上的第一和第二半导体层。构成SRAM中的存储单元的一部分的第一存储单元晶体管具有第一导电类型的第一栅极电极和与第一导电类型相反的第二导电类型的第一源极/漏极扩散层。以下表达式满足第一导电类型的厚度<=第一栅电极在其沟道长度中的长度的三分之一。构成外围电路的一部分的第一外围晶体管具有第三栅极电极和第三源极/漏极扩散层。以下表达式满足第三半导体层的沟道长度方向上的第三栅电极的长度的三分之一的厚度。

10. 发明申请

US20050282354A1 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US20050282354A1
公开(公告)日：2005-12-22
申请号：US11088885
申请日：2005-03-25
申请人： Hirohisa Kawasaki , Kazunari Ishimaru , Kunihiro Kasai , Yasunori Okayama
发明人： Hirohisa Kawasaki , Kazunari Ishimaru , Kunihiro Kasai , Yasunori Okayama
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8238
CPC分类号： H01L29/7842 , H01L21/76208 , H01L21/823807 , H01L21/823878
摘要： A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.
摘要翻译：公开了半导体器件制造方法。该方法是形成与第一半导体层上的第一半导体层相比具有比绝缘特性更小的敏感性的第二半导体层。然后，露出第二和第一半导体层的部分的槽形成为从第二半导体层的上表面延伸到第一半导体层。接下来，暴露于凹槽的第一和第二半导体层的部分被改变为绝缘体形式，以用第一半导体层的绝缘体形式部分填充沟槽。

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