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1. 发明授权

US5886387A BiCMOS semiconductor integrated circuit device having MOS transistor and bipolar transistor regions of different thickness 失效
标题翻译：具有MOS晶体管的BiCMOS半导体集成电路器件和不同厚度的双极晶体管区域
公开(公告)号：US5886387A
公开(公告)日：1999-03-23
申请号：US716729
申请日：1996-09-23
申请人： Masahito Nishigohri , Kazunari Ishimaru
发明人： Masahito Nishigohri , Kazunari Ishimaru
IPC分类号： H01L27/06 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/0623
摘要： Disclosed are a semiconductor integrated circuit device capable of including both a bipolar transistor and a MOS transistor while maintaining high performances of then both and a method of fabricating the device. On a p-type silicon substrate a plurality of n.sup.+ -type regions are formed below the buried collector region of a bipolar transistor and the n-type well region of a MOS transistor. A plurality of p-type regions are formed below the isolation region of the bipolar transistor and the p-type well region of the MOS transistor. An epitaxial layer is formed on the substrate including these n.sup.+ -type and p-type regions. This epitaxial layer forms element region layers having a bipolar transistor region and a MOS transistor region. The thickness of the layer of the bipolar transistor region is smaller than that of the layer of the MOS transistor region.
摘要翻译：公开了一种半导体集成电路器件，其能够包括双极晶体管和MOS晶体管，同时保持两者的高性能，以及制造该器件的方法。在p型硅衬底上，在双极晶体管的掩埋集电极区域和MOS晶体管的n型阱区域的下方形成多个n +型区域。在双极晶体管的隔离区域和MOS晶体管的p型阱区域的下方形成多个p型区域。在包括这些n +型和p型区的衬底上形成外延层。该外延层形成具有双极晶体管区域和MOS晶体管区域的元件区域层。双极晶体管区域的层的厚度小于MOS晶体管区域的厚度。

2. 发明授权

US07164175B2 Semiconductor device with silicon-film fins and method of manufacturing the same 失效
标题翻译：具有硅膜翅片的半导体器件及其制造方法
公开(公告)号：US07164175B2
公开(公告)日：2007-01-16
申请号：US10835122
申请日：2004-04-28
申请人： Hirohisa Kawasaki , Kazunari Ishimaru
发明人： Hirohisa Kawasaki , Kazunari Ishimaru
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0207 , H01L27/11 , H01L27/1108 , H01L27/1211 , H01L29/66795
摘要： A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
摘要翻译：半导体器件包括半导体衬底，投影在半导体衬底的表面上的绝缘膜，设置在绝缘膜的侧表面上的半导体膜和形成在半导体膜中的MIS晶体管，所述MIS晶体管具有源极，栅极和漏区。半导体器件还包括设置在MIS晶体管的栅极区上的栅电极，栅电极的长度大于半导体膜的厚度。

3. 发明申请

US20060278903A1 Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same 失效
标题翻译：在半导体层中具有电致伸缩层的半导体器件及其制造方法
公开(公告)号：US20060278903A1
公开(公告)日：2006-12-14
申请号：US11443430
申请日：2006-05-31
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L29/76 , H01L29/94 , H01L27/108 , H01L31/00 , H01L31/119
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/78 , H01L29/7846
摘要： A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.
摘要翻译：半导体器件包括第一半导体层和设置在第一半导体层的主表面区域中的第一导电类型的第一绝缘栅场效应晶体管。所述半导体器件还包括电致伸缩层，所述电致伸缩层设置在所述第一半导体层的背表面上，并且当所述第一绝缘栅极场中的所述第一绝缘栅场时，沿着沟道长度施加第一应力至所述第一绝缘栅场效应晶体管的沟道区效果晶体管工作。

4. 发明申请

US20060275988A1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060275988A1
公开(公告)日：2006-12-07
申请号：US11404772
申请日：2006-04-17
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/8234 , H01L29/76
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

5. 发明申请

US20060237788A1 Semiconductor device and its fabrication method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060237788A1
公开(公告)日：2006-10-26
申请号：US11364552
申请日：2006-03-01
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/823443 , H01L21/82345 , H01L21/823462
摘要： A semiconductor device has a semiconductor substrate, a first MOSFET which has a first gate insulating film made of a high dielectric material formed above the semiconductor substrate and a first gate electrode formed above the first gate insulating film, an insulating film which is formed directly on sidewalls of the first gate electrode and made of a material having dielectric constant smaller than that of the first gate insulating film, and a second MOSFET which has a second gate insulating film made of a material having dielectric constant smaller than that of the first gate insulating film formed above the semiconductor substrate and a second gate electrode formed above the second gate insulating film, wherein the first gate electrode is formed of a first silicide or a first metal; and the second gate electrode is formed including a film made of at least one of polysilicon, amorphous silicon, polysilicon germanium and amorphous silicon germanium.
摘要翻译：半导体器件具有半导体衬底，第一MOSFET，其具有由半导体衬底上形成的高电介质材料制成的第一栅极绝缘膜和形成在第一栅极绝缘膜上方的第一栅电极，直接形成在绝缘膜上的绝缘膜所述第一栅电极的侧壁由介电常数小于所述第一栅极绝缘膜的介电常数的材料制成;以及第二MOSFET，其具有由介电常数小于所述第一栅极绝缘膜的介电常数的材料制成的第二栅极绝缘膜形成在所述半导体衬底上方的膜和形成在所述第二栅极绝缘膜上方的第二栅电极，其中所述第一栅电极由第一硅化物或第一金属形成; 并且形成第二栅电极，其包括由多晶硅，非晶硅，多晶硅锗和非晶硅锗中的至少一种制成的膜。

6. 发明授权

US07772692B2 Semiconductor device with cooling member 有权
标题翻译：带冷却元件的半导体器件
公开(公告)号：US07772692B2
公开(公告)日：2010-08-10
申请号：US11892808
申请日：2007-08-27
申请人： Tomonao Takamatsu , Hideo Aoki , Kazunari Ishimaru
发明人： Tomonao Takamatsu , Hideo Aoki , Kazunari Ishimaru
IPC分类号： H01L23/34 , H01L23/26
CPC分类号： H01L23/367 , H01L23/3677 , H01L23/3732 , H01L23/3735 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/15311 , H01L2924/16251
摘要： A semiconductor device comprises: a semiconductor element; a mounting substrate with the semiconductor element mounted thereon; a first high thermal conductivity member formed on a surface of the mounting substrate; and a first cooling member thermally connected to at least a part of the first high thermal conductivity member. The first high thermal conductivity member is thermally connected to the semiconductor element, and the first high thermal conductivity member has an outer edge which is located outside an outer edge of the semiconductor element.
摘要翻译：半导体器件包括：半导体元件; 其上安装有半导体元件的安装基板; 形成在所述安装基板的表面上的第一高导热性部件; 以及第一冷却构件，其热连接到所述第一高导热构件的至少一部分。第一高导热性部件热连接到半导体元件，并且第一高导热部件具有位于半导体元件的外边缘外侧的外边缘。

7. 发明授权

US07432542B2 Semiconductor device with electrostrictive layer in semiconductor layer and method of manufacturing the same 失效
标题翻译：在半导体层中具有电致伸缩层的半导体器件及其制造方法
公开(公告)号：US07432542B2
公开(公告)日：2008-10-07
申请号：US11443430
申请日：2006-05-31
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L31/00 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/1203 , H01L29/1054 , H01L29/78 , H01L29/7846
摘要： A semiconductor device includes a first semiconductor layer, and a first insulated-gate field-effect transistor of a first conductivity type that is provided in a major surface region of the first semiconductor layer. The semiconductor device further includes an electrostrictive layer that is provided on a back surface of the first semiconductor layer and applies a first stress along a channel length to a channel region of the first insulated-gate field-effect transistor when the first insulated-gate field-effect transistor is operated.
摘要翻译：半导体器件包括第一半导体层和设置在第一半导体层的主表面区域中的第一导电类型的第一绝缘栅场效应晶体管。所述半导体器件还包括电致伸缩层，所述电致伸缩层设置在所述第一半导体层的背表面上，并且当所述第一绝缘栅极场中的所述第一绝缘栅场时，沿着沟道长度施加第一应力至所述第一绝缘栅场效应晶体管的沟道区效果晶体管工作。

8. 发明授权

US07371644B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07371644B2
公开(公告)日：2008-05-13
申请号：US11404772
申请日：2006-04-17
申请人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
发明人： Atsushi Yagishita , Akio Kaneko , Kazunari Ishimaru
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L21/28097 , H01L21/823431 , H01L27/0886 , H01L29/66795 , H01L29/6681 , H01L29/7851
摘要： According to the present invention, there is provided a semiconductor device fabrication method, comprising: depositing a mask material on a semiconductor substrate; patterning the mask material and forming a trench in a surface portion of the semiconductor substrate by etching, thereby forming a first projection in a first region, and a second projection wider than the first projection in a second region; burying a device isolation insulating film in the trench; etching away a predetermined amount of the device isolation insulating film formed in the first region; etching away the mask material formed in the second region; forming a first gate insulating film on a pair of opposing side surfaces of the first projection, and a second gate insulating film on an upper surface of the second projection; depositing a first gate electrode material on the device isolation insulating film, mask material, and second gate insulating film; planarizing the first gate electrode material by using as stoppers the mask material formed in the first region and the device isolation insulating film formed in the second region; depositing a second gate electrode material on the mask material, first gate electrode material, and device isolation insulating film; and patterning the first and second gate electrode materials, thereby forming a first gate electrode in the first region, and a second gate electrode in the second region.
摘要翻译：根据本发明，提供了一种半导体器件制造方法，包括：在半导体衬底上沉积掩模材料; 图案化掩模材料并通过蚀刻在半导体衬底的表面部分中形成沟槽，从而在第一区域中形成第一突起，在第二区域形成比第一突起宽的第二突起; 在沟槽中埋设器件隔离绝缘膜; 蚀刻形成在第一区域中的预定量的器件隔离绝缘膜; 蚀刻形成在第二区域中的掩模材料; 在所述第一突起的一对相对的侧面上形成第一栅极绝缘膜，在所述第二突起的上表面上形成第二栅极绝缘膜; 在器件隔离绝缘膜，掩模材料和第二栅极绝缘膜上沉积第一栅电极材料; 通过使用形成在第一区域中的掩模材料和形成在第二区域中的器件隔离绝缘膜作为阻挡层来平坦化第一栅电极材料; 在掩模材料上沉积第二栅电极材料，第一栅电极材料和器件隔离绝缘膜; 以及对第一和第二栅电极材料进行构图，从而在第一区域形成第一栅电极，在第二区域形成第二栅电极。

9. 发明申请

US20070007566A1 Semiconductor device having silicide film and method of manufacturing the same 审中-公开
标题翻译：具有硅化物膜的半导体器件及其制造方法
公开(公告)号：US20070007566A1
公开(公告)日：2007-01-11
申请号：US11481592
申请日：2006-07-06
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L29/94
CPC分类号： H01L27/11 , H01L21/823418 , H01L21/823443 , H01L21/823481
摘要： A semiconductor device having a semiconductor substrate, a SRAM area formed in the semiconductor substrate, the SRAM area having first transistors, the first transistor having a metallic compound film formed on each of a source and a drain regions of the first transistor, and a logic circuit area formed in the semiconductor substrate, the logic circuit area having a second transistor, the second transistor having a metallic compound film on each of a source and a drain regions of the second transistor. The thickness of the metallic compound film of the second transistor is thicker than thickness of the metallic compound film of the first transistor.
摘要翻译：一种具有半导体衬底的半导体器件，形成在半导体衬底中的SRAM区域，该SRAM区域具有第一晶体管，该第一晶体管具有形成在第一晶体管的源极和漏极区域中的每一个上的金属化合物膜，以及逻辑电路区域形成在半导体衬底中，逻辑电路区域具有第二晶体管，第二晶体管在第二晶体管的源极和漏极区域中的每个上具有金属化合物膜。第二晶体管的金属化合物膜的厚度比第一晶体管的金属化合物膜的厚度厚。

10. 发明申请

US20060170047A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060170047A1
公开(公告)日：2006-08-03
申请号：US11297636
申请日：2005-12-09
申请人： Kazunari Ishimaru
发明人： Kazunari Ishimaru
IPC分类号： H01L27/12
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L21/82385 , H01L21/823857 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/4933 , H01L29/4975 , H01L29/66772 , H01L29/7833 , H01L29/78654
摘要： A semiconductor device according to an embodiment of the present invention comprises a semiconductor substrate; and a plurality of MOSFETs which are formed on the semiconductor substrate, are the same conductivity type, and have gate insulating films of the same insulating material, with each gate insulating film having any one of a plurality of different thicknesses, and wherein a gate electrode of the MOSFET having a first gate insulating film of a small thickness, consisting substantially of silicide, and a gate electrode of a MOSFET having a second gate insulating film of a thickness larger than that of the first gate insulating film has a structure consisting of polycrystalline silicon, amorphous silicon or silicon-germanium and silicide formed on the polycrystalline silicon, amorphous silicon or germanium silicon.
摘要翻译：根据本发明实施例的半导体器件包括半导体衬底; 并且形成在半导体基板上的多个MOSFET是相同的导电类型，并且具有相同绝缘材料的栅极绝缘膜，每个栅极绝缘膜具有多个不同厚度的任何一个，并且其中栅电极的MOSFET具有基本上由硅化物组成的小厚度的第一栅极绝缘膜，并且具有厚度大于第一栅极绝缘膜的第二栅极绝缘膜的MOSFET的栅电极具有由多晶硅，非晶硅或硅 - 锗和硅化物，形成在多晶硅，非晶硅或锗硅上。

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