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1. 发明申请

US20110260282A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS 审中-公开
标题翻译：半导体器件和制造方法
公开(公告)号：US20110260282A1
公开(公告)日：2011-10-27
申请号：US12766367
申请日：2010-04-23
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L29/66795 , H01L21/76229
摘要： Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed.
摘要翻译：提供制造散热片和包含散热片的半导体结构的方法。所述方法包括在鳍片和隔离材料上形成多层结构，并执行多级蚀刻工艺以去除多层结构的上部和隔离材料的上部。通过多级蚀刻工艺除去隔离材料的上部，使翅片的上部露出。多级蚀刻工艺的阶段除去多层结构的上层和隔离材料的上部，并且阶段可以在多层的下层的下表面的同时终止层结构暴露。

2. 发明授权

US08116121B2 Semiconductor device and manufacturing methods with using non-planar type of transistors 有权
标题翻译：使用非平面型晶体管的半导体器件和制造方法
公开(公告)号：US08116121B2
公开(公告)日：2012-02-14
申请号：US12399197
申请日：2009-03-06
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L21/336
CPC分类号： H01L27/1104 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.
摘要翻译：提供了静态随机存取存储器单元和制造静态随机存取存储单元的方法。静态随机存取存储单元包含两个非平面的通过栅极晶体管，两个非平面上拉晶体管，两个非平面下拉晶体管。非平面上拉晶体管的鳍片的一部分通过辅助杆电连接到非平面下拉晶体管的鳍片的一部分。所述方法包括在非平面上拉晶体管的鳍片和非平面下拉晶体管之间以及栅电极之间形成辅助鳍片，并且扩大辅助鳍片的宽度以形成辅助棒，使得非平面上拉晶体管的鳍片的一部分经由辅助棒电连接到非平面下拉晶体管的鳍片的一部分。

3. 发明授权

US07816739B2 Semiconductor device using SiGe for substrate 失效
标题翻译：半导体器件采用SiGe作为衬底
公开(公告)号：US07816739B2
公开(公告)日：2010-10-19
申请号：US11619799
申请日：2007-01-04
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L29/94
CPC分类号： H01L29/1054 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.
摘要翻译：半导体器件包括第一半导体层，n型/ p型第二半导体层，p型/ n型第三半导体层和第一栅电极。第二半导体层形成在第一半导体层上，其氧化速率低于第一半导体层的氧化速率。第三半导体层形成在第二半导体层中，并且具有到达第一半导体层的内部的深度。在第二和第三半导体层分别为n型和p型的情况下，第二半导体层的晶格常数小于第三半导体层的晶格常数。在第二和第三半导体层分别为p型和n型的情况下，第二半导体层的晶格常数大于第三半导体层的晶格常数。在第二半导体层上形成第一栅电极。

4. 发明申请

US20100224943A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS WITH USING NON-PLANAR TYPE OF TRANSISTORS 有权
标题翻译：半导体器件和使用非平面晶体管的制造方法
公开(公告)号：US20100224943A1
公开(公告)日：2010-09-09
申请号：US12399197
申请日：2009-03-06
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L29/00 , H01L21/00
CPC分类号： H01L27/1104 , H01L21/84 , H01L27/11 , H01L27/1203
摘要： Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar.
摘要翻译：提供了静态随机存取存储器单元和制造静态随机存取存储单元的方法。静态随机存取存储单元包含两个非平面的通过栅极晶体管，两个非平面上拉晶体管，两个非平面下拉晶体管。非平面上拉晶体管的鳍片的一部分通过辅助杆电连接到非平面下拉晶体管的鳍片的一部分。所述方法包括在非平面上拉晶体管的鳍片和非平面下拉晶体管之间以及栅电极之间形成辅助鳍片，并且扩大辅助鳍片的宽度以形成辅助棒，使得非平面上拉晶体管的鳍片的一部分经由辅助棒电连接到非平面下拉晶体管的鳍片的一部分。

5. 发明授权

US07687368B2 Semiconductor device manufacturing method 失效
标题翻译：半导体器件制造方法
公开(公告)号：US07687368B2
公开(公告)日：2010-03-30
申请号：US11088885
申请日：2005-03-25
申请人： Hirohisa Kawasaki , Kazunari Ishimaru , Kunihiro Kasai , Yasunori Okayama
发明人： Hirohisa Kawasaki , Kazunari Ishimaru , Kunihiro Kasai , Yasunori Okayama
IPC分类号： H01L21/76
CPC分类号： H01L29/7842 , H01L21/76208 , H01L21/823807 , H01L21/823878
摘要： A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.
摘要翻译：公开了半导体器件制造方法。该方法是形成与第一半导体层上的第一半导体层相比具有比绝缘特性更小的敏感性的第二半导体层。然后，露出第二和第一半导体层的部分的槽形成为从第二半导体层的上表面延伸到第一半导体层。接下来，暴露于凹槽的第一和第二半导体层的部分被改变为绝缘体形式，以用第一半导体层的绝缘体形式部分填充沟槽。

6. 发明申请

US20070170474A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070170474A1
公开(公告)日：2007-07-26
申请号：US11625985
申请日：2007-01-23
申请人： Hirohisa KAWASAKI
发明人： Hirohisa KAWASAKI
IPC分类号： H01L29/76
CPC分类号： H01L21/823412 , H01L21/823431 , H01L21/823437 , H01L29/7851 , H01L29/7854
摘要： A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a non-planar type transistor region having at least one of a fin type transistor region including a fin type transistor in which a current is induced to flow through side faces of a fin formed approximately vertically to a surface of the semiconductor substrate in a direction approximately parallel to the surface of the semiconductor substrate, and a tri-gate type transistor region including a tri-gate type transistor in which a channel is formed in three surfaces having side faces and an upper surface of a fin formed approximately vertically to the surface of the semiconductor substrate, and thus a current is induced to flow through the three surfaces in a direction approximately parallel to the surface of the semiconductor substrate; and a filling material for isolation in the non-planar type transistor region within the semiconductor substrate and which has a plurality of regions having different heights.
摘要翻译：根据本发明的一个实施例的半导体器件包括：半导体衬底; 一种非平面型晶体管区域，具有包括翅片型晶体管的翅片型晶体管区域中的至少一种，其中电流被引导流过大致垂直于半导体衬底的表面的鳍的侧面，大致垂直于大致平行于半导体衬底的表面的三栅极型晶体管，以及三栅型晶体管区，其包括三栅型晶体管，其中沟道形成在具有侧表面的三个表面中，并且翅片的上表面大致垂直于半导体衬底，从而使电流在大致平行于半导体衬底的表面的方向上流过三个表面; 以及用于在半导体衬底内的非平面型晶体管区域中隔离并且具有多个具有不同高度的区域的填充材料。

7. 发明申请

US20070164364A1 SEMICONDUCTOR DEVICE USING SIGE FOR SUBSTRATE AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：使用基板的信号的半导体器件及其制造方法
公开(公告)号：US20070164364A1
公开(公告)日：2007-07-19
申请号：US11619799
申请日：2007-01-04
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L29/94
CPC分类号： H01L29/1054 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.
摘要翻译：半导体器件包括第一半导体层，n型/ p型第二半导体层，p型/ n型第三半导体层和第一栅电极。第二半导体层形成在第一半导体层上，其氧化速率低于第一半导体层的氧化速率。第三半导体层形成在第二半导体层中，并且具有到达第一半导体层的内部的深度。在第二和第三半导体层分别为n型和p型的情况下，第二半导体层的晶格常数小于第三半导体层的晶格常数。在第二和第三半导体层分别为p型和n型的情况下，第二半导体层的晶格常数大于第三半导体层的晶格常数。在第二半导体层上形成第一栅电极。

8. 发明申请

US20050133819A1 Semiconductor device using strained silicon layer and method of manufacturing the same 审中-公开
标题翻译：使用应变硅层的半导体器件及其制造方法
公开(公告)号：US20050133819A1
公开(公告)日：2005-06-23
申请号：US10972001
申请日：2004-10-25
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/786 , H01L29/10
CPC分类号： H01L21/823807
摘要： A semiconductor device includes a substrate-strained Si formed of a first semiconductor layer which has a first lattice constant and formed on a semiconductor substrate, and a second semiconductor layer which has a second lattice constant and epitaxially grows such that a lattice of the second semiconductor layer matches that of the first semiconductor layer. The semiconductor device further includes a first conductive type metal oxide semiconductor (MOS) transistor which is formed in a first region on the substrate-strained Si and has the second semiconductor layer modified so as to have a first thickness, and a second conductive type MOS transistor which is formed in a second region on the substrate-strained Si and has the second semiconductor layer modified-so as to have a second thickness thinner than the first thickness.
摘要翻译：半导体器件包括由半导体衬底上形成的第一晶格常数的第一半导体层形成的衬底应变Si和具有第二晶格常数并且外延生长的第二半导体层，使得第二半导体层与第一半导体层的匹配。半导体器件还包括第一导电型金属氧化物半导体（MOS）晶体管，该第一导电型金属氧化物半导体（MOS）晶体管形成在基板应变Si上的第一区域中，并且具有被修改为具有第一厚度的第二半导体层，以及第二导电型MOS 晶体管，其形成在衬底应变Si上的第二区域中，并且具有被修改的第二半导体层，以具有比第一厚度更薄的第二厚度。

9. 发明授权

US08809830B2 Variable resistance memory 有权
标题翻译：可变电阻记忆
公开(公告)号：US08809830B2
公开(公告)日：2014-08-19
申请号：US13425668
申请日：2012-03-21
申请人： Hirohisa Kawasaki
发明人： Hirohisa Kawasaki
IPC分类号： H01L45/00
CPC分类号： H01L45/1266 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/148
摘要： A variable resistance memory according to the present embodiment includes a memory cell including an ion source electrode including metal atoms, an opposite electrode, an amorphous silicon film formed between the ion source electrode and the opposite electrode, and a polysilicon film formed between the amorphous silicon film and the ion source electrode.
摘要翻译：根据本实施例的可变电阻存储器包括：存储单元，包括具有金属原子的离子源电极，相对电极，形成在离子源电极和相对电极之间的非晶硅膜;以及形成在非晶硅之间的多晶硅膜膜和离子源电极。

10. 发明申请

US20120193751A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120193751A1
公开(公告)日：2012-08-02
申请号：US13015857
申请日：2011-01-28
申请人： Hirohisa Kawasaki , Basker Veeraraghavan , Hemant Adhikari , Witold Maszara
发明人： Hirohisa Kawasaki , Basker Veeraraghavan , Hemant Adhikari , Witold Maszara
IPC分类号： H01L29/06 , H01L21/20
CPC分类号： H01L29/66795 , H01L29/785
摘要： Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.
摘要翻译：提供制造散热片和包含散热片的半导体结构的方法。所述方法包括在半导体衬底上形成多层结构。多层结构包括半导体衬底上的第一层，第一层上的第二层和第二层上的第三层。该方法还包括去除半导体衬底的上部和多层结构的部分以形成半导体衬底的鳍片和多层结构的部分。此外，该方法包括选择性地氧化第一层，同时氧化第二层，第三层小于第一层的氧化。可以在间隙填充凹部之前或间隙填充凹部之后进行氧化。

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