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    • 1. 发明申请
    • RADIO COMMUNICATION SYSTEM
    • 无线电通信系统
    • WO2008088078A1
    • 2008-07-24
    • PCT/JP2008/051009
    • 2008-01-16
    • MATSUSHITA ELECTRIC WORKS, LTD.SUZUKI, JunichiSAEKI, TakashiSAKAMOTO, KojiKURITA, Masanori
    • SUZUKI, JunichiSAEKI, TakashiSAKAMOTO, KojiKURITA, Masanori
    • G08B25/10
    • G08B25/10G08B17/00G08B25/007
    • A radio communication system minimizes power consumption against noises. The system includes a first radio terminal (10A) with a first transmitter (40A) for transmitting a first data indicative of a specific event, and a second radio terminal (40A) with a battery (14B) and a receiver (20B). The first radio terminal (10A) includes a first bit interpolator (32A) which inserts a check bit pattern of "01010101" at a predetermined cycle into one frame of the first data. The second radio terminal (10B) has a second power controller (60B) which intermittently activates the second receiver (20B) at predetermined intervals in order to receive the bit-interpolated data from the first transmitter. A check bit detector (24B) is included in the second radio terminal (10B) to detect the check bit pattern from within the bit interpolated data and to issue a stop signal immediately upon occurrence of that the check bit pattern fails to appear at said predetermined cycle within a predetermined time frame shorter than one frame length of the first data. In response to the stop signal, the power controller of the second radio terminal terminates a current receiving operation.
    • 无线电通信系统最小化对噪声的功耗。 该系统包括具有用于发送指示特定事件的第一数据的第一发射机(40A)和具有电池(14B)和接收机(20B)的第二无线电终端(40A)的第一无线电终端(10A)。 第一无线电终端(10A)包括第一位内插器(32A),其将预定周期的校验位模式“01010101”插入到第一数据的一帧中。 第二无线电终端(10B)具有以预定间隔间歇地激活第二接收机(20B)的第二功率控制器(60B),以便从第一发射机接收位插值数据。 检查位检测器(24B)包括在第二无线电终端(10B)中,以从位内插数据内检测校验位模式,并且在发生校验位模式不能出现在所述预定位置时立即发出停止信号 在比第一数据的一帧长度短的预定时间范围内循环。 响应于停止信号,第二无线电终端的功率控制器终止当前接收操作。
    • 2. 发明申请
    • WIRELESS FIRE ALARM SYSTEM
    • 无线消防系统
    • WO2008088079A1
    • 2008-07-24
    • PCT/JP2008/051011
    • 2008-01-16
    • MATSUSHITA ELECTRIC WORKS, LTD.SUZUKI, JunichiSAEKI, TakashiSAKAMOTO, KojiKURITA, Masanori
    • SUZUKI, JunichiSAEKI, TakashiSAKAMOTO, KojiKURITA, Masanori
    • G08B1/08G08B25/00
    • G08B25/10G08B25/007
    • A power saving wireless fire alarm system has a master station and a plurality of battery-powered fire detecting terminals linked for wireless communication with each other. Upon detection of a fire occurrence at one of the fire detecting terminals, the fire detecting terminal transmit a fire detection message to a master station which in turn transmit a wake-up message to the other fire detecting terminals and thereafter a fire information message which starts a multiple synchronous communication between the master station and the fire detecting terminals. Each fire detecting terminal has a power controller which selects an intermittent reception mode of activating its own receiver only intermittently until receiving the wake-up message or information indicative of the fire occurrence, and select a constant operation mode thereafter to make the fire detecting terminals be ready for the multiple synchronous communication commenced by the fire information message from the master station.
    • 省电无线火灾报警系统具有主站和多个电池供电的火灾检测终端,用于彼此无线通信链接。 在火灾检测终端中的一个检测到火灾发生时,火情检测终端向主站发送火灾检测消息,主站又向其他火情检测终端发送唤醒消息,之后发送起火信息消息 主站和火灾检测终端之间的多重同步通信。 每个火灾检测终端具有功率控制器,其选择间歇地激活其自己的接收机的间歇接收模式,直到接收到唤醒消息或指示火灾发生的信息,并且此后选择恒定操作模式以使火情检测终端为 准备好从主站的火灾信息消息开始的多个同步通信。
    • 3. 发明申请
    • CONTOUR EMPHASIZING CIRCUIT
    • CONTOUR EMPHISISING CIRCUIT
    • WO1998043412A1
    • 1998-10-01
    • PCT/JP1997000997
    • 1997-03-25
    • FUJITSU GENERAL LIMITEDSUZUKI, SusumuKURITA, Masanori
    • FUJITSU GENERAL LIMITED
    • H04N05/208
    • H04N9/646H04N5/142
    • A contour emphasizing circuit is provided with a number-of-pixels changing circuit (37) which changes the numbers of pixels of digital R, G, and B signals, a gamma correction circuit (39) which performs gamma correction on the output of the circuit (37), a Y-signal generating circuit (36) which generates luminance signals from the output of the circuit (37), an contour extracting circuit (38) which extracts contour components from the output of the circuit (36), a coefficient multiplying circuit (42) which outputs contour components for R, G, and B by multiplying the extracted contour components by coefficients Kr, Kg, and Kb, and contour adding circuits (34r), (34g), and (34b) which respectively add the outputs of the circuits (39 and 42). Thus, the contour emphasizing circuit makes contour emphasis on the digital R, G, and B signals.
    • 轮廓强调电路设置有数字像素改变电路(37),其改变数字R,G和B信号的像素数量;伽马校正电路(39),对伽马校正电路 电路(37),从电路(37)的输出生成亮度信号的Y信号生成电路(36),从电路(36)的输出中提取轮廓成分的轮廓提取电路(38), 系数乘法电路(42),其通过将提取的轮廓分量乘以系数Kr,Kg和Kb以及轮廓加法电路(34r),(34g)和(34b)分别输出用于R,G和B的轮廓分量 添加电路的输出(39和42)。 因此,轮廓强调电路使得轮廓强调数字R,G和B信号。
    • 4. 发明申请
    • CONTOUR EMPHASIZING CIRCUIT
    • CONTOUR EMPHISISR电路
    • WO1998043411A1
    • 1998-10-01
    • PCT/JP1997000996
    • 1997-03-25
    • FUJITSU GENERAL LIMITEDSUZUKI, SusumuKURITA, Masanori
    • FUJITSU GENERAL LIMITED
    • H04N05/208
    • H04N9/646H04N5/208
    • A contour emphasizing circuit provided with a Y-signal generating circuit (36) which generates luminance signals from digital R, G, and B signals, a contour extracting circuit (38) which extracts contour components from the generated Y-signal, a coefficient multiplying circuit (42) which outputs contour components for R, G, and B by multiplying the extracted contour components by coefficients Kr, Kg, and Kb, addition circuits (34r, 34g, and 34b), and a contour emphasis enable circuit (39) which controls the period for which the contour components extracted by the extracting circuit (38) are supplied. Therefore, the contour emphasizing circuit prevents process errors in the peripheral portion of the screen of a display.
    • 一种具有从数字R,G和B信号产生亮度信号的Y信号发生电路(36)的轮廓强调电路,从生成的Y信号中提取轮廓分量的轮廓提取电路(38),系数乘法 电路(42),其通过将提取的轮廓分量乘以系数Kr,Kg和Kb,加法电路(34r,34g和34b)和轮廓强调使能电路(39)来输出R,G和B的轮廓分量, 其控制由提取电路(38)提取的轮廓分量的周期。 因此,轮廓强调电路防止显示器的屏幕的周边部分的处理错误。
    • 5. 发明申请
    • CONTOUR EMPHASIZING CIRCUIT
    • CONTOUR EMPHISISING CIRCUIT
    • WO1998043410A1
    • 1998-10-01
    • PCT/JP1997000995
    • 1997-03-25
    • FUJITSU GENERAL LIMITEDSUZUKI, SusumuKURITA, Masanori
    • FUJITSU GENERAL LIMITED
    • H04N05/208
    • H04N9/646H04N5/142
    • A contour emphasizing circuit which has a first Y-signal generator (35) which generates a luminance signal from digital R, G, and B signals, line memories (31r, 31g and 31b) which delay the R, G and B signals by one line respectively, a second Y-signal generator (37) which generates a luminance signal from the outputs of the line memories, a contour extracting circuit (39) which extracts the vertical contour component and the horizontal contour component, a factor multiplier (42) which multiplies those contour components by factors Kr, Kg and Kb and outputs contour components for R, G and B and contour adders (34r, 34g and 34b) which add the contour components for R, G and B to the R, G and B signals respectively.
    • 一种轮廓强调电路,具有从数字R,G和B信号产生亮度信号的第一Y信号发生器(35),将R,G和B信号延迟一个的行存储器(31r,31g和31b) 分别产生来自行存储器的输出的亮度信号的第二Y信号发生器(37),提取垂直轮廓分量和水平轮廓分量的轮廓提取电路(39),因子乘法器(42) 它们将这些轮廓分量乘以因子Kr,Kg和Kb,并输出R,G和B的轮廓分量,以及将R,G和B的轮廓分量添加到R,G和B的轮廓加法器(34r,34g和34b) 信号。
    • 8. 发明申请
    • PLL CIRCUIT FOR DIGITAL DISPLAY DEVICE
    • 用于数字显示设备的PLL电路
    • WO1998007272A1
    • 1998-02-19
    • PCT/JP1996003395
    • 1996-11-20
    • FUJITSU GENERAL LIMITEDNISHIMURA, EizoKONDOU, SatoruKURITA, Masanori
    • FUJITSU GENERAL LIMITED
    • H04N05/12
    • G09G5/008H03L7/0807H03L7/095H03L7/199H04N5/126H04N5/66
    • A PLL circuit is provided with a lock/unlock detecting circuit which detects the locked or unlocked state of the PLL circuit by comparing the phases of a horizontal synchronizing signal and a comparing signal with each other and an internal synchronizing signal generating circuit which outputs the comparing signal as an internal synchronizing signal when the locked state is detected or outputs the horizontal synchronizing signal as the internal synchronizing signal when the unlocked state is detected. Another mode of a PLL circuit is provided with a skew detecting circuit which resets a frequency dividing circuit upon detecting a skew which is deviated from a normal period in an external synchronizing signal, generates a dummy pulse upon detecting that no skew occurs in the external synchronizing signal in the normal period, and generates a reference signal in combination of the dummy pulse with the external synchronizing signal. When the skew detecting circuit detects a skew, the circuit also resets a phase comparator circuit. A digital display device having such a PLL circuit prevents distortion of the picture when the PLL circuit is in an unlocked state or a skew occurs.
    • PLL电路具有锁定/解锁检测电路,其通过将水平同步信号和比较信号的相位进行比较来检测PLL电路的锁定或解锁状态,以及内部同步信号发生电路,其输出比较 当检测到锁定状态时,将其作为内部同步信号,或者当检测到解锁状态时输出水平同步信号作为内部同步信号。 PLL电路的另一模式设置有偏斜检测电路,其在检测到在外部同步信号中与正常周期偏离的偏斜时复位分频电路,在检测到外部同步中不发生偏斜时产生虚拟脉冲 在正常周期中产生信号,并且产生与虚拟脉冲和外部同步信号组合的参考信号。 当偏斜检测电路检测到偏斜时,电路还复位相位比较器电路。 具有这种PLL电路的数字显示装置防止当PLL电路处于解锁状态或发生偏斜时图像的失真。