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1. 发明申请

WO1998007272A1 PLL CIRCUIT FOR DIGITAL DISPLAY DEVICE 审中-公开
标题翻译：用于数字显示设备的PLL电路
公开(公告)号：WO1998007272A1
公开(公告)日：1998-02-19
申请号：PCT/JP1996003395
申请日：1996-11-20
申请人： FUJITSU GENERAL LIMITED , NISHIMURA, Eizo , KONDOU, Satoru , KURITA, Masanori
发明人： FUJITSU GENERAL LIMITED
IPC分类号： H04N05/12
CPC分类号： G09G5/008 , H03L7/0807 , H03L7/095 , H03L7/199 , H04N5/126 , H04N5/66
摘要： A PLL circuit is provided with a lock/unlock detecting circuit which detects the locked or unlocked state of the PLL circuit by comparing the phases of a horizontal synchronizing signal and a comparing signal with each other and an internal synchronizing signal generating circuit which outputs the comparing signal as an internal synchronizing signal when the locked state is detected or outputs the horizontal synchronizing signal as the internal synchronizing signal when the unlocked state is detected. Another mode of a PLL circuit is provided with a skew detecting circuit which resets a frequency dividing circuit upon detecting a skew which is deviated from a normal period in an external synchronizing signal, generates a dummy pulse upon detecting that no skew occurs in the external synchronizing signal in the normal period, and generates a reference signal in combination of the dummy pulse with the external synchronizing signal. When the skew detecting circuit detects a skew, the circuit also resets a phase comparator circuit. A digital display device having such a PLL circuit prevents distortion of the picture when the PLL circuit is in an unlocked state or a skew occurs.
摘要翻译： PLL电路具有锁定/解锁检测电路，其通过将水平同步信号和比较信号的相位进行比较来检测PLL电路的锁定或解锁状态，以及内部同步信号发生电路，其输出比较当检测到锁定状态时，将其作为内部同步信号，或者当检测到解锁状态时输出水平同步信号作为内部同步信号。 PLL电路的另一模式设置有偏斜检测电路，其在检测到在外部同步信号中与正常周期偏离的偏斜时复位分频电路，在检测到外部同步中不发生偏斜时产生虚拟脉冲在正常周期中产生信号，并且产生与虚拟脉冲和外部同步信号组合的参考信号。当偏斜检测电路检测到偏斜时，电路还复位相位比较器电路。具有这种PLL电路的数字显示装置防止当PLL电路处于解锁状态或发生偏斜时图像的失真。

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