PURPOSE:To speed up 2N-bit multiplication only by adding slight hardware by providing a detecting means for all-1 and all-0 states of high-order N-bits of a multiplier and a multiplicand, and controlling the frequency of the N-bit multiplication according to its detection result. CONSTITUTION:Lines 2a and 2b, and 3a and 3b are both input data lines with N- bit width and a high-order and a low-order N-bit line of 2N bits. Detecting circuits 22a and 22b detect N-bit parts of the input data lines 3a and 2a are in the all-1 or all-0 state. A selecting circuit 29 selects the input data line 2a or 2b to supply its data to an input A of a multiplying circuit 5, and a selecting circuit 30 selects the input data line 3a or 3b to supply its data to an input B of the multiplying circuit. A control signal 31 has four states, and the selecting circuits 29 and 30 select input data XL or XH, and YL or YH according to the state of the control signal and the bit pattern of YL.