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    • 4. 发明申请
    • SYSTEMS AND METHODS THAT EMPLOY INDUCTIVE CURRENT STEERING FOR DIGITAL LOGIC CIRCUITS
    • 使用数字逻辑电路的感应电流转向系统和方法
    • WO2005072496A2
    • 2005-08-11
    • PCT/US2005/000864
    • 2005-01-10
    • NORTHROP GRUMMAN CORPORATIONNOTTHOFF, Johannes, K.
    • NOTTHOFF, Johannes, K.
    • H03K3/2885H03K17/041
    • H03K17/04113H03K3/2885
    • The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is "on" while the other is "off," which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters. Further, the systems and methods can be utilized to construct flip-flops and shift registers by coupling differential transistor pairs and driving these pairs with the transformer-based single-ended or differential clock.
    • 本发明提供了利用感应电流转向来减轻与常规晶体管电流转向相关联的传播延迟来提高逻辑电路性能的系统和方法。 该系统和方法采用RF变压器,其中激励初级绕组在相关联的次级绕组中感应电流。 在一个方面,使用单个时钟总线来感应电流,该电流通过次级绕组的相应端被引导到晶体管的发射极引线。 该电流和电压是异相180度,使得一个晶体管“导通”,而另一个晶体管为“关闭”,其产生差分输出。 在另一方面,采用差分时钟信号来感应次级绕组和相关晶体管发射极中的电流。 此外,系统和方法可以用于通过耦合差分晶体管对来构造触发器和移位寄存器,并使用基于变压器的单端或差分时钟驱动这些对。
    • 5. 发明申请
    • CONTROL LOOP FOR MINIMAL TAILNODE EXCURSION OF DIFFERENTIAL SWITCHES
    • 控制环路用于微小开关的极小截止点
    • WO2004015866A3
    • 2004-05-06
    • PCT/US0323021
    • 2003-07-23
    • ANALOG DEVICES INC
    • SCHAFFERER BERND
    • H03K17/041H03K17/16H03K17/693H03M1/08H03M1/74H03K17/687
    • H03K17/165H03K17/04106H03K17/693H03M1/0863H03M1/742
    • A system and method are provided for controlling the on/off timing relationship between two transistors (202a, 202b) in a differential that are connected at a tail node (207) to a common current generator (204, 206). The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to drive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals. An embodiment that adjusts the voltage of the on/off signals to control the on/off timing is also disclosed.
    • 提供了一种用于控制在尾节点(207)连接到公共电流发生器(204,206)的差分中的两个晶体管(202a,202b)之间的开/关定时关系的系统和方法。 开/关定时关系由控制晶体管状态的开/关信号控制,使得一个晶体管转而另一个晶体管截止。 从尾部节点偏移导出重叠信号,并且指示开/关信号是否重叠太多或太少。 基于重叠信号生成控制信号。 基于控制信号调整用于驱动开/关信号的驱动信号的定时。 当需要更多重叠时,调整驱动器信号的定时,使得导出的开/关信号的重叠更多。 当需要较少的重叠时,调整驱动器信号的定时,使得导出的开/关信号的重叠较少。 还公开了调整开/关信号的电压以控制开/关定时的实施例。
    • 6. 发明申请
    • COMPARATOR WITH VERY FAST REGENERATION TIME CONSTANT
    • 具有非常快速再生时间的比较器
    • WO03017485A3
    • 2003-10-16
    • PCT/US0225907
    • 2002-08-13
    • HRL LAB LLCCOSAND ALBERT E
    • COSAND ALBERT E
    • H03K3/2885H03K3/356H03K17/041H03K17/0416
    • H03K3/2885H03K3/356043H03K17/04113H03K17/04166
    • A comparator comprises a cross-coupled regenerative latch, a circuit connected to thecross-coupled regenerative latch and a clocking circuit. The cross-coupled regenerative latch regenerates, during a latching mode, a signal which is indicative of a difference between two input signals. The circuit connected to the cross-coupled regenerative latch operates as a voltage follower during an acquisition mode and as a cascode amplifier stage during the latching mode. The clocking circuit switches the comparator from the acquisition mode to the latching mode and vice versa. The comparator eleminates the extraneous loading from the positive feedback when the regeneration takes place, so that a very fast regeneration time constant is obtained.
    • 比较器包括交叉耦合再生锁存器,连接到交叉耦合再生锁存器的电路和时钟电路。 交叉耦合再生锁存器在锁存模式期间再生指示两个输入信号之间的差异的信号。 连接到交叉耦合再生锁存器的电路在采集模式期间作为电压跟随器工作,在锁存模式期间用作共源共栅放大器级。 时钟电路将比较器从采集模式切换到锁存模式,反之亦然。 当再生发生时,比较器从正反馈中解除外部负载,从而获得非常快的再生时间常数。