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1. 发明申请

WO01018962A1 FLIP-FLOP CIRCUIT, AND METHOD OF HOLDING AND SYNCHRONIZING DATA USING CLOCK SIGNAL 审中-公开
标题翻译： FLIP-FLOP电路，以及使用时钟信号保存和同步数据的方法
公开(公告)号：WO01018962A1
公开(公告)日：2001-03-15
申请号：PCT/JP2000/005924
申请日：2000-08-31
IPC分类号： H03K19/086 , H03K3/286 , H03K3/2885 , H03K3/289
CPC分类号： H03K3/289 , H03K3/2885
摘要： A low-power, high-speed flip-flop circuit is provided that has a simplified, smaller circuit configuration. A flip-flop comprises two latch hold circuits composed of transistors (B1-B4) and transistors (B5-B8), respectively; and a clock-input differential circuit composed of transistors (B9-B12). With clock inputs (CP) and (CN) being high and low, respectively, transistors (B9, B10) turn on, and the current from a constant current source (12) turns transistor (B2, B3) off. Similarly, transistors (B5, B8) are also turned off, causing the second latch hold circuit to be in hold state. With clock inputs (CP) and (CN) being low and high, respectively, the states of the first and second latch hold circuits are switched, resulting in flip-flop operation.
摘要翻译：提供了一种具有简化的较小电路配置的低功率，高速触发器电路。触发器分别包括由晶体管（B1-B4）和晶体管（B5-B8）组成的两个锁存保持电路; 和由晶体管（B9-B12）组成的时钟输入差分电路。随着时钟输入（CP）和（CN）分别为高电平和低电平，晶体管（B9，B10）导通，来自恒流源（12）的电流使晶体管（B2，B3）断开。类似地，晶体管（B5，B8）也被截止，使得第二锁存保持电路处于保持状态。在时钟输入（CP）和（CN）分别为低电平和高电平时，第一和第二锁存保持电路的状态被切换，导致触发器操作。

2. 发明申请

WO2012000715A1 ELEKTRONISCHE SCHALTUNG ZUR OPTISCHEN ANSTEUERUNG EINES FLIP FLOP 审中-公开
标题翻译：电子电路对触发器的光学控制
公开(公告)号：WO2012000715A1
公开(公告)日：2012-01-05
申请号：PCT/EP2011/058061
申请日：2011-05-18
申请人： ROHDE & SCHWARZ GMBH & CO. KG , LANDOLT, Oliver
发明人： LANDOLT, Oliver
IPC分类号： H03K3/42 , H03K3/2885
CPC分类号： H03K17/78 , H03K3/2885 , H03K3/42
摘要： Eine elektronische Schaltung beinhaltet eine Kippschaltung (13), einen Schalter (12), eine Photodiode (14) und einen modengekoppelten Laser (10). Der modengekoppelte Laser (10) erzeugt Lichtpulse, welche in der Photodiode (14) einen Photostrom erzeugen. Der Schalter (12) überträgt den Photostrom an einen von zwei Eingängen (R', S') der Kippschaltung (13). Die Kippschaltung (13) gibt seinen Zustand an zumindest einem Ausgang (Q') aus.
摘要翻译：一种电子电路，包括一个触发器（13），开关（12），光电二极管（14）和一个锁模激光器（10）。锁模激光（10），生成产生在光电二极管（14）的光电流的光脉冲。所述开关（12）发送该多谐振荡器（13）的光电流对的两个输入之一（R“ S”）。触发器（13）处于其状态从至少一个输出（Q“）。

3. 发明申请

WO2006079966A3 DEVICE COMPRISING A LATCH 审中-公开
标题翻译：包含闩锁的装置
公开(公告)号：WO2006079966A3
公开(公告)日：2006-10-12
申请号：PCT/IB2006050242
申请日：2006-01-23
申请人： KONINKL PHILIPS ELECTRONICS NV , SANDULEANU MIHAI A T , STIKVOORT EDUARD F , TOMBEUR ANTOON M H
发明人： SANDULEANU MIHAI A T , STIKVOORT EDUARD F , TOMBEUR ANTOON M H
IPC分类号： H03K3/2885
CPC分类号： H03K3/2885
摘要： Devices (101-105) comprising latches (1-3) with tracking circuits (4) for, in tracking modes, tracking data signals and with deciding circuits (5) for, in deciding modes, deciding about the data signal can use their available time more efficiently by, in the tracking modes, preparing the deciding circuits (5). Thereto, the deciding circuits (5) are not to be switched between disabled/enabled situations, but are to be kept enabled. The tracking circuits (4), in the tracking modes, supply signal values derived from the data signals to the deciding circuits (5), and the deciding circuits (5), in the deciding modes, amplify the signal values. The tracking circuits (4) comprise diodes (21,22) to allow reduced voltage swings in the data signals to be sufficient for proper performances of the latch (1-3). Such reduced voltage swings allow the latches (1-3) to perform at higher speeds. The parasitic capacitors present between the cathodes of the diodes (21,22) form capacitances for storing the signal values and allow the deciding circuits (5) to be prepared.
摘要翻译：包括具有跟踪电路（4）的锁存器（1-3）的设备（101）用于在跟踪模式中跟踪数据信号并且与决定电路（5）用于在决定模式时决定数据信号可以使用它们的可用通过在跟踪模式中准备决定电路（5）更有效。此外，决定电路（5）不在禁用/启用情况之间切换，而是保持启用状态。跟踪电路（4）在跟踪模式中将来自数据信号的信号值提供给决定电路（5），决定电路（5）在决定模式中放大信号值。跟踪电路（4）包括二极管（21,22），以允许数据信号中的电压摆动减小足以使锁存器（1-3）的适当性能。这种减小的电压摆动允许锁存器（1-3）以更高的速度执行。存在于二极管（21,22）的阴极之间的寄生电容器形成用于存储信号值的电容并允许准备确定电路（5）。

4. 发明申请

WO2005072496A3 SYSTEMS AND METHODS THAT EMPLOY INDUCTIVE CURRENT STEERING FOR DIGITAL LOGIC CIRCUITS 审中-公开
标题翻译：使用数字逻辑电路的感应电流转向系统和方法
公开(公告)号：WO2005072496A3
公开(公告)日：2006-04-06
申请号：PCT/US2005000864
申请日：2005-01-10
申请人： NORTHROP GRUMMAN CORP , NOTTHOFF JOHANNES K
发明人： NOTTHOFF JOHANNES K
IPC分类号： H03K3/2885 , H03K17/041 , H02H7/00 , H03K17/16 , H03K19/094 , H03L7/00
CPC分类号： H03K17/04113 , H03K3/2885
摘要： The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is "on" while the other is "off," which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters. Further, the systems and methods can be utilized to construct flip-flops and shift registers by coupling differential transistor pairs and driving these pairs with the transformer-based single-ended or differential clock.
摘要翻译：本发明提供了利用感应电流转向来减轻与常规晶体管电流转向相关联的传播延迟来提高逻辑电路性能的系统和方法。该系统和方法采用RF变压器，其中激励初级绕组在相关联的次级绕组中感应电流。在一个方面，使用单个时钟总线来感应电流，该电流通过次级绕组的相应端被引导到晶体管的发射极引线。该电流和电压是异相180度，使得一个晶体管“导通”，而另一个晶体管为“关闭”，其产生差分输出。在另一方面，采用差分时钟信号来感应次级绕组和相关晶体管发射极中的电流。此外，系统和方法可以用于通过耦合差分晶体管对来构造触发器和移位寄存器，并使用基于变压器的单端或差分时钟驱动这些对。

5. 发明申请

WO2022005645A1 T-SWITCH WITH SHUNT FOR IMPROVED RECEIVER SENSITIVITY 审中-公开
公开(公告)号：WO2022005645A1
公开(公告)日：2022-01-06
申请号：PCT/US2021/033917
申请日：2021-05-24
申请人： QUALCOMM INCORPORATED
发明人： DABBAGH REZAEI, Vahid , ABBAS MOHAMED HELMY, Ahmed , THOPPAY EGAMBARAM, Prakash
IPC分类号： H04B1/06 , H03K17/00 , H04Q11/04 , H04B1/44 , H03K3/2885 , H04B1/006 , H04L25/24 , H04Q11/0421 , H04Q2213/13098
摘要： Aspects of the disclosure relate to devices, wireless communication apparatuses, methods, and circuitry for a t-switch with gate shunting. One aspect is an apparatus including a first differential switch having a control input. The apparatus further includes a second differential switch coupled to the first differential switch, the second differential switch a control input. A shunt capacitor is coupled between a first output and a second output of the first differential switch, and a first input and a second input of the second differential switch. A first shunt switch having a control input, an input, and an output has the input and the output coupled to the control input of the first differential switch. A second shunt switch having a control input, an input, and an output, has the input and the output coupled to the control input of the second differential switch.

6. 发明申请

WO2011036212A1 STATIC FREQUENCY DIVIDER CIRCUITRY 审中-公开
标题翻译：静态分频电路
公开(公告)号：WO2011036212A1
公开(公告)日：2011-03-31
申请号：PCT/EP2010/064056
申请日：2010-09-23
申请人： TECHNISCHE UNIVERSITÄT DRESDEN , CAI, Weiran , ELLINGER, Frank
发明人： CAI, Weiran , ELLINGER, Frank
IPC分类号： H03K3/2885 , H03K3/289
CPC分类号： H03K3/2885 , H03K3/289
摘要： The present invention relates to a static frequency divider circuitry comprising a delay flip-flop related structure. An object of the present invention is to design a frequency divider circuitry that meets upcoming low power requirements without introducing special design constrains, working at supply voltage significantly lower than 3.0V and operation frequencies comparable to the current state of the art. This object is achieved through providing a static frequency comprising a delay flip-flop related structure including a master part and a slave part being operated by clock transistors arranged as emitter followers of the common collector transistors, combined to control both the master part and the slave part of the frequency divider by sharing one clock switch and one inverse clock switch and a latching unit being either a virtual latching unit capable to temporarily store charges or a real latching unit consisting of proper latching devices.
摘要翻译：本发明涉及一种包括延迟触发器相关结构的静态分频器电路。本发明的目的是设计一种分频器电路，可以满足即将到来的低功率需求，而不会引入特别的设计限制，工作电压明显低于3.0V，工作频率与当前技术水平相当。该目的通过提供一种静态频率来实现，该静态频率包括延迟触发器相关结构，包括主器件和从器件，其由布置为公共集电极晶体管的发射极跟随器的时钟晶体管操作，被组合以控制主器件和从器件通过共享一个时钟开关和一个反相时钟切换器以及一个可以临时存储电荷的虚拟锁存单元的锁存单元或由适当的锁存装置组成的真实锁存单元来分频器的一部分。

7. 发明申请

WO2006079966A2 DEVICE COMPRISING A LATCH 审中-公开
标题翻译：包含锁扣的装置
公开(公告)号：WO2006079966A2
公开(公告)日：2006-08-03
申请号：PCT/IB2006/050242
申请日：2006-01-23
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , TOMBEUR, Antoon, M., H.
发明人： SANDULEANU, Mihai, A., T. , STIKVOORT, Eduard, F. , TOMBEUR, Antoon, M., H.
IPC分类号： H03K3/2885
CPC分类号： H03K3/2885
摘要： Devices (101-105) comprising latches (1-3) with tracking circuits (4) for, in tracking modes, tracking data signals and with deciding circuits (5) for, in deciding modes, deciding about the data signal can use their available time more efficiently by, in the tracking modes, preparing the deciding circuits (5). Thereto, the deciding circuits (5) are not to be switched between disabled/enabled situations, but are to be kept enabled. The tracking circuits (4), in the tracking modes, supply signal values derived from the data signals to the deciding circuits (5), and the deciding circuits (5), in the deciding modes, amplify the signal values. The tracking circuits (4) comprise diodes (21,22) to allow reduced voltage swings in the data signals to be sufficient for proper performances of the latch (1-3). Such reduced voltage swings allow the latches (1-3) to perform at higher speeds. The parasitic capacitors present between the cathodes of the diodes (21,22) form capacitances for storing the signal values and allow the deciding circuits (5) to be prepared.
摘要翻译：包括具有跟踪电路（4）的锁存器（101-105），跟踪电路（4）用于在跟踪模式下跟踪数据信号，并且在判定模式下用决定电路（5）决定数据信号可以使用它们的可用在跟踪模式下，更准确地准备决定电路（5）。此外，决定电路（5）不能在禁用/启用状态之间切换，而是被保持启用。跟踪电路（4）在跟踪模式中，将从数据信号导出的信号值提供给判定电路（5），并且判定模式中的判定电路（5）放大信号值。跟踪电路（4）包括二极管（21,22），以允许数据信号中的减小的电压摆动对于锁存器（1-3）的适当性能是足够的。这种减小的电压摆动允许闩锁（1-3）以更高的速度执行。存在于二极管（21,22）的阴极之间的寄生电容器形成用于存储信号值的电容，并允许准备决定电路（5）。

8. 发明申请

WO2005072496A2 SYSTEMS AND METHODS THAT EMPLOY INDUCTIVE CURRENT STEERING FOR DIGITAL LOGIC CIRCUITS 审中-公开
标题翻译：使用数字逻辑电路的感应电流转向系统和方法
公开(公告)号：WO2005072496A2
公开(公告)日：2005-08-11
申请号：PCT/US2005/000864
申请日：2005-01-10
申请人： NORTHROP GRUMMAN CORPORATION , NOTTHOFF, Johannes, K.
发明人： NOTTHOFF, Johannes, K.
IPC分类号： H03K3/2885 , H03K17/041
CPC分类号： H03K17/04113 , H03K3/2885
摘要： The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, wherein energizing primary windings induce current in associated secondary windings. In one aspect, a single clock bus is employed to induce the current, which is routed via respective ends of the secondary winding to emitter leads of the transistors. This current and voltage is 180 degrees out-of-phase such that one transistor is "on" while the other is "off," which generates a differential output. In another aspect, a differential clock signal is employed to induce the current in secondary windings and associated transistor emitters. Further, the systems and methods can be utilized to construct flip-flops and shift registers by coupling differential transistor pairs and driving these pairs with the transformer-based single-ended or differential clock.
摘要翻译：本发明提供了利用感应电流转向来减轻与常规晶体管电流转向相关联的传播延迟来提高逻辑电路性能的系统和方法。该系统和方法采用RF变压器，其中激励初级绕组在相关联的次级绕组中感应电流。在一个方面，使用单个时钟总线来感应电流，该电流通过次级绕组的相应端被引导到晶体管的发射极引线。该电流和电压是异相180度，使得一个晶体管“导通”，而另一个晶体管为“关闭”，其产生差分输出。在另一方面，采用差分时钟信号来感应次级绕组和相关晶体管发射极中的电流。此外，系统和方法可以用于通过耦合差分晶体管对来构造触发器和移位寄存器，并使用基于变压器的单端或差分时钟驱动这些对。

9. 发明申请

WO03017485A3 COMPARATOR WITH VERY FAST REGENERATION TIME CONSTANT 审中-公开
标题翻译：具有非常快速再生时间的比较器
公开(公告)号：WO03017485A3
公开(公告)日：2003-10-16
申请号：PCT/US0225907
申请日：2002-08-13
申请人： HRL LAB LLC , COSAND ALBERT E
发明人： COSAND ALBERT E
IPC分类号： H03K3/2885 , H03K3/356 , H03K17/041 , H03K17/0416
CPC分类号： H03K3/2885 , H03K3/356043 , H03K17/04113 , H03K17/04166
摘要： A comparator comprises a cross-coupled regenerative latch, a circuit connected to thecross-coupled regenerative latch and a clocking circuit. The cross-coupled regenerative latch regenerates, during a latching mode, a signal which is indicative of a difference between two input signals. The circuit connected to the cross-coupled regenerative latch operates as a voltage follower during an acquisition mode and as a cascode amplifier stage during the latching mode. The clocking circuit switches the comparator from the acquisition mode to the latching mode and vice versa. The comparator eleminates the extraneous loading from the positive feedback when the regeneration takes place, so that a very fast regeneration time constant is obtained.
摘要翻译：比较器包括交叉耦合再生锁存器，连接到交叉耦合再生锁存器的电路和时钟电路。交叉耦合再生锁存器在锁存模式期间再生指示两个输入信号之间的差异的信号。连接到交叉耦合再生锁存器的电路在采集模式期间作为电压跟随器工作，在锁存模式期间用作共源共栅放大器级。时钟电路将比较器从采集模式切换到锁存模式，反之亦然。当再生发生时，比较器从正反馈中解除外部负载，从而获得非常快的再生时间常数。

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