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1. 发明申请

WO2019243578A1 KERAMISCHES VIELSCHICHTBAUELEMENT UND VERFAHREN ZUR HERSTELLUNG EINES KERAMISCHEN VIELSCHICHTBAUELEMENTS 审中-公开
公开(公告)号：WO2019243578A1
公开(公告)日：2019-12-26
申请号：PCT/EP2019/066476
申请日：2019-06-21
申请人： TDK ELECTRONICS AG
发明人： HOFSTÄTTER, Michael , HOFRICHTER, Alfred , FEICHTINGER, Thomas
IPC分类号： H01C7/00 , H01C7/02 , H01C7/04 , H01C7/10 , H01C7/18 , H01G4/30 , H01G4/005 , H01G4/012 , H01G4/12 , H01C17/065 , H01C17/28 , H01G4/232 , H01C1/14 , H01G4/008
摘要： Es wird ein keramisches Vielschichtbauelement (100) angegeben, das einen Stapel (1) mit keramischen Schichten (2) und dazwischen angeordneten Elektrodenschichten (3, 4) aufweist, wobei die keramischen Schichten und die Elektrodenschichten entlang einer Stapelrichtung (S) übereinander angeordnet sind, wobei sich zumindest eine erste Elektrodenschicht (3) entlang einer Haupterstreckungsrichtung (H) von einem ersten Endbereich (31) zu einem zweiten Endbereich (32) der ersten Elektrodenschicht erstreckt und wobei die zumindest eine Elektrodenschicht eine sich entlang der HäupterStreckungsrichtung verringernde Stromtragfähigkeit aufweist. Weiterhin wird ein Verfahren zur Herstellung eines keramischen VielSchichtbauelements angegeben.

2. 发明申请

WO2018193402A1 PHASE ANGLE TUNABLE FRACTIONAL-ORDER CAPACITORS INCLUDING MULTI-LAYER FERROELECTRIC POLYMER DIELECTRIC AND METHODS OF MANUFACTURE THEREOF 审中-公开
公开(公告)号：WO2018193402A1
公开(公告)日：2018-10-25
申请号：PCT/IB2018/052733
申请日：2018-04-19
申请人： SABIC GLOBAL TECHNOLOGIES, B.V.
发明人： SALAMA, Khaled Nabil , AGAMBAYEV, Agamyrat , BAGCI, Hakan , FARHAT, Mohamed , PATOLE, Shashikant
IPC分类号： H01G4/18 , H01G4/33 , H01G4/008 , H01G4/012
CPC分类号： H01G4/186 , H01G4/008 , H01G4/012 , H01G4/33 , H01G7/06
摘要： Discussed herein are embodiments of fractional-order capacitors (FOC) and methods of manufacture thereof such that the FOC is tuned to a value or to fall within a predetermined value such as a phase angle. The FOCs are designed and fabricate with dielectric layers of an interlayer structure of two or more individual layers of poly(vinylidene fluoride (P(VDF)) ("P"), ferroelectric poly(vinylidene fluoride trifluoroethylene P(VDF-TrFE) ("CP"), or ferroelectric poly(vinylidene fluoride terpolymer P(VDF-TrFE-CFE) ("TP"). Each layer of an interlayer structure of a dielectric layer may differ from at least one other layer in one of material, composition of solution used to form the layer, and/or thickness.

3. 发明申请

WO2017155854A1 MULTI-LAYER ELECTRONIC DEVICE 审中-公开
标题翻译：多层电子器件
公开(公告)号：WO2017155854A1
公开(公告)日：2017-09-14
申请号：PCT/US2017/020869
申请日：2017-03-06
申请人： AVX CORPORATION
发明人： RITTER, Andrew P. , BEROLINI, Marianne
IPC分类号： H01G4/012 , H01G4/12 , H01G4/30
摘要： A multi-layer electronic device is disclosed that comprises a ceramic layer, a first electrode layer, and a second electrode layer. The first electrode layer contains a first tab portion extending to the first lateral edge of the ceramic layer, the first electrode layer further defining a first cut-out region. The second electrode layer contains a second tab portion extending to the first lateral edge of the ceramic layer, the second electrode layer further defining a second cut-out region. The first tab portion of the first electrode layer is offset from the second tab portion of the second electrode layer in the longitudinal direction so that a first gap region is formed within which the first tab portion does not overlap the second tab portion. Further, the first cut-out region at least partially overlaps the second cut-out region.
摘要翻译：公开了一种多层电子器件，其包括陶瓷层，第一电极层和第二电极层。第一电极层包含延伸到陶瓷层的第一侧边缘的第一接线片部分，第一电极层进一步限定第一切除区域。第二电极层含有延伸到陶瓷层的第一横向边缘的第二接线片部分，第二电极层进一步限定第二切除区域。第一电极层的第一接线片部分在纵向方向上偏离第二电极层的第二接线片部分，从而形成第一间隙区域，第一接线片部分不与第二接线片部分重叠。此外，第一切除区域至少部分地与第二切除区域重叠。

4. 发明申请

WO2015105719A1 ACOUSTIC NOISE CANCELLATION IN MULTI-LAYER CAPACITORS 审中-公开
标题翻译：多层电容器中的声音噪声消除
公开(公告)号：WO2015105719A1
公开(公告)日：2015-07-16
申请号：PCT/US2014/072978
申请日：2014-12-31
申请人： APPLE INC.
发明人： KOLLER, Jeffrey G. , UNGAR, P. Jeffrey
IPC分类号： H01G4/012 , H01G4/30 , H01G4/35 , H01G4/38 , H01G4/40 , H02M1/12 , G05F1/10 , H01G4/12
CPC分类号： H01G4/30 , G05F1/10 , H01G4/012 , H01G4/12 , H01G4/35 , H01G4/38 , H01G4/40 , H02M1/12 , H02M3/04
摘要： A device is presented for decoupling voltage transients occurring on a voltage signal generated by a voltage regulator. The dev ice may decouple the voltage transients from circuits coupled to the voltage regulator. The device may include two capacitors that may be contained in a single package. The two capacitors may be coupled to the voltage signal from the voltage regulator such that one capacitor is also coupled to a ground reference and the other capacitor is also coupled to a supply voltage. The capacitors may be constructed in a multi-layer ceramic capacitor (MLCC) process. The materials that form the MLCC may be arranged such that the MLCC package does not change shape or vibrate in response to voltage level fluctuations on the voltage signal.
摘要翻译：提出了一种用于去耦合由电压调节器产生的电压信号上发生的电压瞬变的器件。开关冰可以将电压瞬变与耦合到电压调节器的电路分离。该装置可以包括可以包含在单个封装中的两个电容器。两个电容器可以耦合到来自电压调节器的电压信号，使得一个电容器也耦合到接地基准，而另一个电容器也耦合到电源电压。电容器可以由多层陶瓷电容器（MLCC）制造。形成MLCC的材料可以被布置成使得MLCC封装不响应于电压信号上的电压电平波动而改变形状或振动。

5. 发明申请

WO2012107349A1 ELEKTRISCHES KERAMIKBAUELEMENT MIT ELEKTRISCHER ABSCHIRMUNG 审中-公开
标题翻译：随着电动盾电器陶瓷元件
公开(公告)号：WO2012107349A1
公开(公告)日：2012-08-16
申请号：PCT/EP2012/051786
申请日：2012-02-02
申请人： EPCOS AG , FEICHTINGER, Thomas , KRENN, Georg , KUDLATY, Jerzy
发明人： FEICHTINGER, Thomas , KRENN, Georg , KUDLATY, Jerzy
IPC分类号： H01C7/18 , H01G4/012 , H01G4/30
CPC分类号： H05K7/00 , H01C7/18 , H01G4/012 , H01G4/30
摘要： Das elektrische Keramikbauelement besitzt einen Grundkörper (9) aus dielektrischem Material, in dem ein aktiver Bereich (3) angeordnet ist. Mindestens ein Außenkontakt (1, 1') ist an dem Grundkörper angeordnet. Ein Zuleitungsbereich (2, 2') verbindet den Außenkontakt mit dem aktiven Bereich. Eine Elektrode (4, 4', 5, 5', 6, 6') ist benachbart zu dem Zuleitungsbereich in dem Grundkörper angeordnet und mit dem Außenkontakt, aber nicht mit dem aktiven Bereich, elektrisch leitend verbunden.
摘要翻译：电陶瓷元件具有电介质材料制成的基体（9），其中有源区（3）被布置。至少一个外触头（1,1“）布置在所述基体上。的供给区域（2,2“）连接与有源区外接触。的电极（4,4“ 5，5' ，6,6”）邻近于设置在所述基体和连接到所述外触头的馈线部分，但不与所述有源区，导电的。

6. 发明申请

WO2012038695A1 A MULTIFUNCTION CHARGE TRANSFER DEVICE 审中-公开
标题翻译：多功能充电传输装置
公开(公告)号：WO2012038695A1
公开(公告)日：2012-03-29
申请号：PCT/GB2011/001366
申请日：2011-09-20
申请人： MANTOCK, Paul Lenworth
发明人： MANTOCK, Paul Lenworth
IPC分类号： H01G4/26 , H01G4/005 , H01G4/012
CPC分类号： H01G4/06 , H01G4/005 , H01G4/012 , H01G4/26
摘要： A multifunction charge transfer device that limits and controls a current and voltage to a circuit or load, comprising at least one input and at least one output electrode as the charging electrode (10a) and the discharging electrode (10b) respectively, both in the form of closed continuous electrical loops. The charging electrode (10a) and discharging electrode (10b) in the form of closed continuous electrical loops are arranged side by side so that the edges of the electrical conducting material and the dielectric material (11a, lib) forming each closed continuous electrical loop are in alignment. The two closed continuous electrical loops are separated by a gap (12) to prevent any electrical contact between them and so that the charging electrode (10a) and discharging electrode (10b) can only be coupled by the electrostatic field concentrated at the side of the closed continuous electrical loop forming the charging electrode (10a). The charging and discharging electrodes (10a, 10b) are each provided with connectors (13a, 13b) respectively as a means for connection to an electric circuit in series.
摘要翻译：一种多功能电荷转移装置，其限制并控制电路或负载的电流和电压，分别包括至少一个输入和至少一个输出电极作为充电电极（10a）和放电电极（10b）的闭合连续电气回路。闭合连续电气回路形式的充电电极（10a）和放电电极（10b）并排布置，使得导电材料和形成每个封闭的连续电气回路的电介质材料（11a，lib）的边缘是对齐。两个闭合的连续电气回路由间隙（12）隔开，以防止它们之间的任何电接触，从而充电电极（10a）和放电电极（10b）只能通过集中在形成充电电极（10a）的封闭连续电路。充电和放电电极（10a，10b）分别设有连接器（13a，13b）作为用于连接到电路的装置。

7. 发明申请

WO2012018701A1 VERTICAL CAPACITORS FORMED ON SEMICONDUCTING SUBSTRATES 审中-公开
标题翻译：形成半导体衬底的垂直电容
公开(公告)号：WO2012018701A1
公开(公告)日：2012-02-09
申请号：PCT/US2011/046067
申请日：2011-08-01
申请人： HARRIS CORPORATION
发明人： SMITH, David, M.
IPC分类号： H01L21/02 , H01G4/012 , H01G4/30 , H01L23/522
CPC分类号： H01L23/5223 , H01G4/012 , H01G4/306 , H01L28/86 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： Semiconductor devices (100) and methods of making the same are disclosed. Each of the semiconductor devices includes a substrate (102) having a first surface (118) and an opposing second surface. A vertical capacitive element (104) is disposed on the first surface of the substrate. The vertical capacitive element comprises a plurality of parallel conductive plates (120a, 120b,...) extending transverse to the first surface of the substrate. Adjacent conductive plates are spaced a distance D from each other. A dielectric material (110) is disposed in a space separating the adjacent conductive plates. Each of the conductive plates has a height -to width (h/w) ratio greater than or equal to one.
摘要翻译：公开了半导体器件（100）及其制造方法。每个半导体器件包括具有第一表面（118）和相对的第二表面的衬底（102）。垂直电容元件（104）设置在基板的第一表面上。垂直电容元件包括横向于衬底的第一表面延伸的多个平行导电板（120a，120b，...）。相邻的导电板彼此间隔开距离D. 介电材料（110）设置在分隔相邻导电板的空间中。每个导电板的高度 - 宽度（h / w）比都大于或等于1。

8. 发明申请

WO2007071096A1 AN ELECTRODES ARRANGEMENT BUSHING AND A METHOD OF USING A BUSHING 审中-公开
标题翻译：电极布置布置和使用布置的方法
公开(公告)号：WO2007071096A1
公开(公告)日：2007-06-28
申请号：PCT/CH2006/000722
申请日：2006-12-20
申请人： ABB RESEARCH LTD , CARLEN, Martin , CHRISTEN, Thomas , FUHRMANN, Henning , VOTTELER, Torsten
发明人： CARLEN, Martin , CHRISTEN, Thomas , FUHRMANN, Henning , VOTTELER, Torsten
IPC分类号： H01G4/012 , H01G4/228 , H01B17/36
CPC分类号： H01G4/32 , H01B17/28 , H01G4/228
摘要： A bushing comprises an electrode configuration with a film (1), which film (1) comprises a base (2) consisting of an electrically insulating polymer which carries on one- or both surfaces a sequence of electrically conductively coated areas (3) which are separated by non-coated interstices (4). The film or a superposition of films arranged one above the other is wound to form an electrode configuration with a plurality of essentially parallel electrodes which are insulated from each other and consist each of one or more electrode layers formed by the coated areas (3) and separated by insulating layers formed by sections of the base (2). An electrode layer may comprise two adjacent coated areas pertaining to subsequent turns. The electrode configuration can be used to subdivide a potential difference, e.g., in a bushing, into a series of smaller potential differences between subsequent electrodes, with the smaller potential differences preferably smaller than the minimum of the Paschen curve.
摘要翻译：衬套包括具有膜（1）的电极构造，该膜（1）包括由电绝缘聚合物构成的基体（2），所述电绝缘聚合物在一个或两个表面上承载一系列导电涂覆区域（3）由无涂层间隙（4）隔开。缠绕形成具有多个彼此绝缘的多个基本上平行的电极的电极构造的膜或叠加在一起的薄膜或叠层，并且包括由涂覆区域（3）形成的一个或多个电极层和由基部（2）的部分形成的绝缘层分隔开。电极层可以包括与后续匝相关的两个相邻的涂覆区域。电极配置可用于将电位差（例如在衬套中）细分成后续电极之间的一系列较小的电位差，较小的电位差优选小于帕邢曲线的最小值。

9. 发明申请

WO00033335A1 FOIL FOR A FOIL CAPACITOR AND FOIL CAPACITOR 审中-公开
标题翻译：薄膜的薄膜电容器和薄膜电容器
公开(公告)号：WO00033335A1
公开(公告)日：2000-06-08
申请号：PCT/CH1999/000573
申请日：1999-12-01
IPC分类号： H01G4/012 , H01G4/015 , H01G9/145
CPC分类号： H01G4/012
摘要： The invention relates to a foil for a foil capacitor, comprising an electrically insulating carrier foil with an electroconductive layer placed thereon. The electroconductive layer in the foil capacitor forms an electrode and the carrier foil forms a dielectric. The invention is characterized in that the electroconductive layer (2) is as thin as possible and that at least one current path (4, 5) is provided in order to reduce the overall surface resistance on the electroconductive layer (2). Said current path has a lower surface resistance than the electroconductive layer.
摘要翻译：公开了一种用于薄膜电容器，其是具有在其上涂覆导电层，该导电层的电极和形成在薄膜电容器的介电载体膜的电绝缘载体膜形成的膜。本发明的特征在于，所述导电层被形成为尽可能薄（2），并且，为了减少（2）的至少一个电流路径（4,5）被设置在导电层具有比较低的表面电阻的总的薄层电阻具有导电层。

10. 发明申请

WO2022154510A1 적층형 세라믹 콘덴서 및 이를 구비한 파워 모듈 审中-公开
公开(公告)号：WO2022154510A1
公开(公告)日：2022-07-21
申请号：PCT/KR2022/000630
申请日：2022-01-13
申请人： 주식회사 아모텍
发明人： 구유경 , 이재욱
IPC分类号： H01G4/30 , H01G4/012 , H01G4/12
摘要： 세라믹 콘덴서에 상부 전극 및 하부 전극을 형성하여 파워 모듈에 실장이 용이하면서 기생 성분의 발생을 최소화하도록 한 적층형 세라믹 콘덴서를 제시한다. 제시된 적층형 세라믹 콘덴서는 내부에 복수의 내부 전극이 배치된 유전체, 유전체의 제1 측면에 배치된 제1 외부 전극, 유전체의 제2 측면에 배치된 제2 외부 전극, 유전체의 상면에 배치되고, 유전체의 제1 측면에 인접하여 배치되어 제1 외부 전극과 연결된 상부 전극 및 유전체의 하면에 배치되고, 유전체의 제2 측면에 인접하여 배치되어 제2 외부 전극과 연결된 하부 전극을 포함한다.

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