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1. 发明申请

WO1996008039A1 STRUCTURE AND FABRICATION OF BIPOLAR TRANSISTORS 审中-公开
标题翻译：双极晶体管的结构和制造
公开(公告)号：WO1996008039A1
公开(公告)日：1996-03-14
申请号：PCT/US1995011145
申请日：1995-08-31
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , BULUCEA, Constantin , GRUBISICH, Michael, J.
IPC分类号： H01L29/732
CPC分类号： H01L29/66272 , H01L29/1004 , Y10S148/01
摘要： A special two-dimensional intrinsic base doping profile is utilized to improve the output current-voltage characteristics of a vertical bipolar transistor whose intrinsic base includes a main intrinsic portion (64M). The special doping profile is achieved with a pair of more lightly doped base portions (66) that encroach substantially into the intrinsic base below the main intrinsic base portion (64M). The two deep encroaching base portions (66) extend sufficiently close to each other to set up a two-dimensional charge-sharing mechanism that typically raises the magnitude of the punch-through voltage. The transistor's current-voltage characteristics are thereby enhanced. Manufacture of the transistor entails introducing suitable dopants into a semiconductor body. In one fabrication process, a fast-diffusing dopant is employed in forming the deep encroaching base portions (66) without significantly affecting earlier-created transistor regions.
摘要翻译：使用特殊的二维本征基极掺杂分布来改善其本征基极包括主本征部分（64M）的垂直双极晶体管的输出电流 - 电压特性。特殊的掺杂分布是通过一对更轻掺杂的基底部分（66）实现的，该基部分基本上侵入主本征基底部分（64M）之下的本征基底。两个深侵入基部（66）彼此充分地延伸，以建立二维电荷共享机构，其通常提高穿通电压的大小。从而提高了晶体管的电流 - 电压特性。晶体管的制造需要将合适的掺杂剂引入半导体本体。在一个制造工艺中，快速扩散掺杂剂用于形成深侵入基部（66），而不会明显影响早先产生的晶体管区域。

2. 发明申请

WO1993008599A1 BIPOLAR JUNCTION TRANSISTOR EXHIBITING IMPROVED BETA AND PUNCH-THROUGH CHARACTERISTICS 审中-公开
标题翻译：双极晶体管显示改进的BETA和PUNCH-THROUGH特性
公开(公告)号：WO1993008599A1
公开(公告)日：1993-04-29
申请号：PCT/US1992008905
申请日：1992-10-19
申请人： MICROUNITY SYSTEMS ENGINEERING, INC.
发明人： MICROUNITY SYSTEMS ENGINEERING, INC. , MATTHEWS, James, A.
IPC分类号： H01L23/00
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/36 , H01L29/732 , Y10S148/01
摘要： A bipolar transistor having an emitter (25), a base (31), and a collector (30) includes an intrinsic base (33) region having narrow side areas (p-) and a wider central area (37). The side areas are located adjacent to the extrinsic base region (31), while the central area (37) is disposed underneath the emitter (25). The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region (31) and the central area (37) are relatively high compared to the doping concentration of the narrow side areas (p-) of the intrinsic base (33). The combination of the narrow side areas (p-) and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.
摘要翻译：具有发射极（25），基极（31）和集电极（30）的双极晶体管包括具有窄侧面积（p-）和较宽中心区域（37）的本征基极（33）区域。侧面区域邻近外部基极区域（31）定位，而中心区域（37）设置在发射器（25）的下方。定制基底的横向掺杂分布，使得非本征区域（31）和中心区域（37）中的掺杂浓度相对于本征基底的窄边区域（p-）的掺杂浓度相对较高 33）。窄边区域（p-）和横向基极掺杂曲线的组合限制了基极内的耗尽区域，从而降低晶体管的穿通电压而不损失β。

3. 发明申请

WO9615549A2 USE OF OBLIQUE IMPLANTATION IN FORMING BASE OF BIPOLAR TRANSISTOR 审中-公开
标题翻译：在形成双极晶体管的基础上使用OBLIQUE植入
公开(公告)号：WO9615549A2
公开(公告)日：1996-05-23
申请号：PCT/US9514625
申请日：1995-10-12
申请人： NAT SEMICONDUCTOR CORP
发明人： HUNG-SHENG CHEN , TENG CHIH SIEH
IPC分类号： H01L21/331 , H01L
CPC分类号： H01L29/66272 , Y10S148/01 , Y10S438/965
摘要： In fabricating a bipolar transistor, semiconductor dopant is introduced into a semiconductor body during a base doping operation to define a doped region, part of which constitutes a base region for the transistor. The base doping operation entails ion implanting the dopant into the body at a tilt angle of at least 15 DEG relative to the vertical. The minimum lateral base thickness and, when the base region abuts a slanted sidewall of a field insulating region, the minimum sidewall base thickness increase relative to the minimum vertical base thickness. As a result, the magnitude of the collector-to-emitter breakdown voltage typically increases. The minimum lateral, sidewall, and vertical base thicknesses vary with the tilt angle and base-implant energy in such a manner that the minimum lateral base thickness and the minimum sidewall base thickness are separately controllable from the minimum vertical base thickness.
摘要翻译：在制造双极晶体管时，在基极掺杂操作期间将半导体掺杂剂引入到半导体本体中以限定掺杂区域，其中的一部分构成晶体管的基极区域。基极掺杂操作需要以相对于垂直方向至少15°的倾斜角将掺杂剂离子注入到体内。最小横向基底厚度，并且当基部区域邻接场绝缘区域的倾斜侧壁时，最小侧壁基底厚度相对于最小垂直基底厚度增加。结果，集电极 - 发射极击穿电压的大小通常增加。最小横向，侧壁和垂直基底厚度随着倾斜角和基底植入能量的变化，使得最小横向基底厚度和最小侧壁基底厚度可以从最小垂直基底厚度分开控制。

4. 发明申请

WO1995023430A1 BIPOLAR AND BICMOS STRUCTURES AND METHODS OF FABRICATION 审中-公开
标题翻译： BIPOLAR和BICMOS结构和制造方法
公开(公告)号：WO1995023430A1
公开(公告)日：1995-08-31
申请号：PCT/US1994010482
申请日：1994-09-16
申请人： NATIONAL SEMICONDUCTOR CORPORATION
发明人： NATIONAL SEMICONDUCTOR CORPORATION , GRUBISICH, Michael, J.
IPC分类号： H01L21/82
CPC分类号： H01L27/0623 , H01L21/8249 , Y10S148/009 , Y10S148/01
摘要： In a bipolar or BiCMOS process, a heavily doped buried layer (140) of a first conductivity type and a heavily doped channel stop region (150) of a second conductivity type are formed in a lightly doped substrate (120) of the second conductivity type. A lightly doped epitaxial layer (210) of the first conductivity type is grown. An implant (250) of the first conductivity type creates a guard ring around the bipolar transistor active region and also creates a higher-doped collector region inside the active region. In the BiCMOS process, during the formation of CMOS wells (310, 520), a silicon nitride mask (230) over the bipolar transistor inhibits oxidation of the epitaxial layer and the oxidation-enhanced diffusion of the buried layer. As a result, the epitaxial layer can be made thinner, reducing the collector resistance. The MOS transistor wells can be formed without an underlying buried layer, simplifying the process and decoupling the bipolar and MOS transistor characteristics from each other. A heavy implant of the second conductivity type creates a field implant region (840.1) around each transistor. Around the bipolar transistor, the field implant region meets the channel stop region. Field oxide (830) is grown over the field implant region by LOCOS process. A base region (940) is formed inside the guard ring.
摘要翻译：在双极或BiCMOS工艺中，在第二导电类型的轻掺杂衬底（120）中形成第一导电类型的重掺杂掩埋层（140）和第二导电类型的重掺杂沟道截止区（150）。生长第一导电类型的轻掺杂外延层（210）。第一导电类型的注入（250）在双极晶体管有源区周围产生保护环，并且还在有源区内部产生较高掺杂的集电极区域。在BiCMOS工艺中，在CMOS阱（310,520）的形成期间，双极晶体管上方的氮化硅掩模（230）抑制外延层的氧化和掩埋层的氧化增强的扩散。结果，可以使外延层更薄，从而降低集电极电阻。可以形成MOS晶体管阱，而不需要下层掩埋层，简化工艺并将双极和MOS晶体管特性互相解耦。第二导电类型的重注入在每个晶体管周围产生场注入区域（840.1）。在双极晶体管周围，场注入区域与沟道停止区域相交。场氧化物（830）通过LOCOS工艺在场注入区域上生长。在保护环内部形成基部区域（940）。

5. 发明申请

WO1997024757A1 A METHOD OF MANUFACTURING A SELF-ALIGNED VERTICAL BIPOLAR TRANSISTOR ON AN SOI 审中-公开
标题翻译：在SOI上制造自对准的垂直双极晶体管的方法
公开(公告)号：WO1997024757A1
公开(公告)日：1997-07-10
申请号：PCT/IB1996001397
申请日：1996-12-09
申请人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB
发明人： PHILIPS ELECTRONICS N.V. , PHILIPS NORDEN AB , KIM, Manvin, J.
IPC分类号： H01L21/33
CPC分类号： H01L29/66265 , Y10S148/01 , Y10S148/15
摘要： A process is set forth for providing a self-aligned, vertical bipolar SOI transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications such as MMIC devices. A microwave transistor is provided by this technique.
摘要翻译：阐述了提供自对准的垂直双极型SOI晶体管的过程。提供了一种控制技术，用于提供晶体管的基极和发射极特征，其适当的尺寸和性质可用于高频微波应用（如MMIC器件）。通过这种技术提供微波晶体管。

6. 发明申请

WO1996010839A1 A METHOD OF FABRICATING A BIPOLAR JUNCTION TRANSISTOR 审中-公开
标题翻译：一种双极晶体晶体管的制作方法
公开(公告)号：WO1996010839A1
公开(公告)日：1996-04-11
申请号：PCT/US1995011921
申请日：1995-09-20
申请人： UNITED TECHNOLOGIES CORPORATION
发明人： UNITED TECHNOLOGIES CORPORATION , JEROME, Rick, C. , POST, Ian, R., C.
IPC分类号： H01L21/331
CPC分类号： H01L29/66272 , H01L21/2257 , H01L21/8228 , Y10S148/01 , Y10S148/011
摘要： The present invention teaches a method for fabricating a bipolar junction transistor ("BJT") from a semiconductor substrate having a base region, wherein the BJT comprises an increased Early voltage. The method initially comprises the step of forming a patterned interlevel dielectric layer superjacent the substrate such that a segment of the substrate is exposed. Subsequently, a contact comprising a material having a grain size smaller than polycrystalline silicon is formed superjacent the patterned interlevel dielectric layer and the segment of the substrate exposed. The contact is then implanted with a dopant. Once implanted, the substrate is annealed to enable the dopant to diffuse from the contact into the base region impeded by the grain size to form an emitter region and thereby increase the Early voltage of the bipolar junction transistor.
摘要翻译：本发明教导了一种从具有基极区域的半导体衬底制造双极结型晶体管（“BJT”）的方法，其中BJT包括增加的早期电压。该方法最初包括以下步骤：在衬底之上形成图案化的层间电介质层，使得衬底的一部分被暴露。随后，包含具有小于多晶硅的晶粒尺寸的材料的触点形成在图案化的层间电介质层的上方，并且衬底的部分被暴露。然后用掺杂剂注入接触。一旦被植入，衬底被退火以使掺杂剂从接触扩散到由晶粒尺寸阻挡的基极区域中，以形成发射极区域，从而增加双极结型晶体管的早期电压。

7. 发明申请

WO1991005365A1 A SEMICONDUCTOR DEVICE FABRICATION PROCESS 审中-公开
标题翻译：半导体器件制造工艺
公开(公告)号：WO1991005365A1
公开(公告)日：1991-04-18
申请号：PCT/GB1990001528
申请日：1990-10-04
申请人： SEAGATE MICROELECTRONICS LTD. , RODRIGUES, Richard, Anthony, Alexis , GILLESPIE, Ewen
发明人： SEAGATE MICROELECTRONICS LTD.
IPC分类号： H01L21/033
CPC分类号： H01L21/761 , H01L21/033 , H01L21/743 , H01L21/8222 , Y10S148/01 , Y10S148/163
摘要： A semiconductor device fabrication process in which the features of a composite mask are transferred to a first covering on a surface of a semiconductor bulk, the first covering is etched to provide windows for the introduction of impurities into the semiconductor bulk, and selected windows in the first covering are masked by a second covering differing in composition from the first covering, to facilitate the introduction of impurities through open windows in the first covering into the semiconductor bulk.

8. 发明申请

WO1987006764A1 PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：制造半导体器件的工艺
公开(公告)号：WO1987006764A1
公开(公告)日：1987-11-05
申请号：PCT/US1987000766
申请日：1987-03-31
申请人： AMERICAN TELEPHONE & TELEGRAPH COMPANY
发明人： AMERICAN TELEPHONE & TELEGRAPH COMPANY , CHIU, Tzu-Yin , CHIN, Gen, Man , HANSON, Ronald, Curtis , LAU, Maureen, Y. , LEE, Kwing, Fai , MORRIS, Mark, D. , VOSHCHENKOV, Alexander, Michael
IPC分类号： H01L21/82
CPC分类号： H01L29/41783 , H01L21/2257 , H01L21/32155 , H01L21/8249 , H01L27/0623 , Y10S148/009 , Y10S148/01 , Y10S148/124 , Y10S148/151
摘要： A process for creating bipolar and CMOS transistors on a p-type silicon substrate. The silicon substrate has typical n+ buried wells and field oxide regions to isolate the individual transistor devices. In accordance with the process, stacks (51, 52, 53) of material are created over the gate elements of the CMOS devices and over the emitter elements of the bipolar transistors. The stacks of material over the gate elements have a silicon dioxide gate layer (17) in contact with the epitaxial layer of the substrate, and the stacks of material over the emitter elements have a polycrystalline silicon layer (32) in contact with the epitaxial layer. Walls (61) of silicon dioxide are created around the stacks in order to insulate the material within the stacks from the material deposited outside of the walls. Polycrystalline silicon (81) in contact with the epitaxial layer is deposited outside the walls surrounding the stacks. All polycrystalline silicon layers in contact with the epitaxial layer are implanted with appropriate dopants such that these layers serve as reservoirs of dopant in order to simultaneously create the source and drain elements of the CMOS devices and the emitter elements of the bipolar devices during a heating step in the process. A tungsten layer is deposited over the polycrystalline layer in order to provide a conductive coupling to aluminum electrodes.
摘要翻译：在p型硅衬底上制造双极和CMOS晶体管的工艺。硅衬底具有典型的n +掩埋阱和场氧化物区域以隔离各个晶体管器件。根据该过程，材料的堆叠（51,52,53）在CMOS器件的栅极元件上以及双极晶体管的发射极元件之上产生。在栅极元件上方的堆叠材料具有与衬底的外延层接触的二氧化硅栅极层（17），并且发射极元件上的堆叠材料具有与外延层接触的多晶硅层（32）。在堆叠周围形成二氧化硅的壁（61），以使堆叠内的材料与沉积在壁外部的材料绝缘。与外延层接触的多晶硅（81）沉积在堆叠周围的壁的外部。与外延层接触的所有多晶硅层都注入合适的掺杂剂，使得这些层用作掺杂剂的储存器，以便在加热步骤期间同时产生CMOS器件的源极和漏极元件以及双极器件的发射极元件正在进行中。为了提供与铝电极的导电耦合，在多晶层上沉积钨层。

9. 发明申请

WO1982000385A1 METHOD AND MEANS OF RESISTIVELY CONTACTING AND INTERCONNECTING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：电阻接触和互连半导体器件的方法和手段
公开(公告)号：WO1982000385A1
公开(公告)日：1982-02-04
申请号：PCT/US1981000928
申请日：1981-07-10
申请人： UNIV LELAND STANFORD JUNIOR
发明人： UNIV LELAND STANFORD JUNIOR , MALTIEL R
IPC分类号： H01L21/263
CPC分类号： H01L29/0847 , H01L21/76886 , H01L23/522 , H01L23/647 , H01L27/0629 , H01L28/20 , H01L29/167 , H01L29/32 , H01L29/8605 , H01L2924/0002 , Y10S148/01 , Y10S148/024 , Y10S257/902 , H01L2924/00
摘要： Resistive elements of semiconductor devices and integrated circuits are reduced in size thereby allowing larger scale integration. Deep level dopants including impurities or crystalline lattice defects, or both, are formed in a low resistance doped region thereby increasing the resistance of a portion of the doped region. Resistive contacts and interconnects require less semiconductor surface area.

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