专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2016027981A1 비이진 부호의 단축 및 천공 방법 및 장치 审中-公开
标题翻译：用于封装和打包非二进制码的方法和装置
公开(公告)号：WO2016027981A1
公开(公告)日：2016-02-25
申请号：PCT/KR2015/006947
申请日：2015-07-06
申请人： 삼성전자주식회사
发明人： 안석기 , 박우명 , 사공민 , 임치우 , 홍성남
IPC分类号： H03M13/11
CPC分类号： H03M13/31 , H03M13/1171 , H03M13/255 , H03M13/618 , H03M13/6362 , H03M13/6393 , H04L1/00 , H04L1/0013 , H04L1/0041 , H04L1/0069
摘要： 본 개시는 LTE와 같은 4G 통신 시스템 이후 보다 높은 데이터 전송률을 지원하기 제공될 5G 또는 pre-5G 통신 시스템에 관련된 것이다. 본 발명은 비이진 LDPC 부호의 효율적인 단축 및 천공 방법 및 장치에 관한 것으로서, 비이진 부호를 단축 및 천공하기 위한 송신단의 방법은 비이진 부호를 구성하는 적어도 하나의 정보 심볼에서 변조 방식을 기반으로 적어도 하나의 정보 비트를 단축하는 과정과, 상기 정보 비트가 단축된 적어도 하나의 정보 심볼을 인코딩하는 과정과, 상기 인코딩을 통해 획득된 적어도 하나의 패리티 심볼에서 상기 변조 방식을 기반으로 적어도 하나의 패리티 코드를 천공하는 과정을 포함하여, 단일 비이진 부호를 이용하여 다양한 변조 방식을 지원할 수 있다.
摘要翻译：本公开涉及要在诸如LTE的4G通信系统之后提供的用于支持更高数据传输速率的5G或5G以前的5G通信系统。本发明涉及一种用于有效地缩短和删截非二进制LDPC码的方法和装置，该发射机缩短和穿孔非二进制码的方法能够通过使用单个非二进制码来支持各种调制方法并且所述方法包括以下步骤：根据调制方法缩短构成所述非二进制码的至少一个信息符号中的至少一个信息比特; 编码具有缩短的信息比特的所述至少一个信息符号; 以及基于所述调制方法，通过所述编码步骤获得的至少一个奇偶校验符号中的至少一个奇偶校验码进行删截。

2. 发明申请

WO2013147774A1 PROCESSING ELEMENTARY CHECK NODES OF AN ITERATIVE DECODER 审中-公开
标题翻译：处理元素检查迭代解码器的编号
公开(公告)号：WO2013147774A1
公开(公告)日：2013-10-03
申请号：PCT/US2012/031031
申请日：2012-03-28
申请人： INTEL CORPORATION , KWOK, Zion, S
发明人： KWOK, Zion, S
IPC分类号： H03M13/00
CPC分类号： H03M13/09 , H03M13/1117 , H03M13/1171
摘要： Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了以节省计算资源的方式处理与迭代解码器相关联的基本校验节点的设备，装置，方法，计算机可读介质和系统配置。在各种实施例中，可以接收第一和第二组m个元组，例如作为基本校验节点的输入。每个元组可以包括符号和符号正确的概率，并且第一和第二组m个元组可以通过它们各自的概率进行排序。在各种实施例中，可以计算少于m个组的第一组和第二组的所有组合，以便作为基本校验节点的输出考虑，并且可以将一些计算的组合作为输出从考虑中消除。在各种实施例中，基本校验节点可输出具有最高概率的一组m个输出元组。可以描述和/或要求保护其他实施例。

3. 发明申请

WO2012164528A1 METHOD FOR UPDATING A FACTOR GRAPH OF AN A POSTERIORI PROBABILITY ESTIMATOR 审中-公开
标题翻译：用于更新一个POSTERIORI概率估计器的因子图的方法
公开(公告)号：WO2012164528A1
公开(公告)日：2012-12-06
申请号：PCT/IB2012/052754
申请日：2012-05-31
申请人： POLITECNICO DI TORINO , MONTORSI, Guido
发明人： MONTORSI, Guido
IPC分类号： G06N7/00 , H03M13/11
CPC分类号： G06N7/005 , H03M13/1117 , H03M13/1171
摘要： A method is described for updating a factor graph (10;10';10") of an a posteriori probability estimator, said factor graph comprising at least one repetition node (13;13';13") and at least one sum node (11;11';11"), wherein at least two connections are associated with each node, and wherein each connection is associated with an incoming message at said node and with an outgoing message from said node, wherein said method comprises the steps of: storing the nodes' incoming and outgoing messages into memory means (12;12';12") of said estimator as messages belonging to one same class of wrapped and/ or sampled Gaussian messages; updating said node of said factor graph (10;10';10") by using a resulting message belonging to said class of incoming messages, said resulting message being obtained by processing said incoming wrapped and/ or sampled Gaussian messages.
摘要翻译：描述了一种用于更新后验概率估计器的因子图（10; 10'; 10“）的方法，所述因子图包括至少一个重复节点（13; 13'; 13”）和至少一个和节点 11; 11'; 11“），其中至少两个连接与每个节点相关联，并且其中每个连接与所述节点处的输入消息和来自所述节点的输出消息相关联，其中所述方法包括以下步骤：将所述节点的输入和输出消息存储在所述估计器的存储器装置（12; 12'; 12“）中，作为属于同一类别的包裹和/或采样高斯消息的消息; 通过使用属于所述类别的输入消息的结果消息来更新所述因子图（10; 10'; 10“）的所述节点，所述结果消息通过处理所述传入的包裹和/或采样高斯消息而获得。

4. 发明申请

WO2009120952A3 APPARATUS AND METHOD FOR DECODING SIGNALS 审中-公开
标题翻译：用于解码信号的装置和方法
公开(公告)号：WO2009120952A3
公开(公告)日：2010-02-18
申请号：PCT/US2009038542
申请日：2009-03-27
申请人： THOMSON LICENSING , MUELLER STEFAN , KRAVTCHENKO ALEXANDER , KLINKE STANISLAW , LOPRESTO SCOTT
发明人： MUELLER STEFAN , KRAVTCHENKO ALEXANDER , KLINKE STANISLAW , LOPRESTO SCOTT
IPC分类号： H04N7/24 , H04N7/015
CPC分类号： H03M13/1171 , H03M13/258 , H03M13/3944 , H03M13/395
摘要： In accordance with an aspect of the present embodiments, a method of decoding a bitstream is described including receiving a demodulated bitstream, the demodulated bitstream encoded using a byte-code encoding process, arranging a portion of the demodulated bitstream into a subset of bits, reordering the subset of bits, and decoding the subset of bits based on a property of the reordered subset of bits and the byte- code encoding process.
摘要翻译：根据本实施例的一个方面，描述了对比特流进行解码的方法，包括：接收解调比特流，使用字节码编码处理编码的解调比特流，将解调比特流的一部分排列成比特的子集，重新排序比特的子集，以及基于比特的重新排序的子集和字节码编码处理的属性来解码比特的子集。

5. 发明申请

WO2008035133A1 MULTIPLE-INPUT-MULTIPLE-OUTPUT TRANSMISSION USING NON-BINARY LDPC CODING 审中-公开
标题翻译：使用非二进制LDPC编码的多输入多输出传输
公开(公告)号：WO2008035133A1
公开(公告)日：2008-03-27
申请号：PCT/IB2006/003620
申请日：2006-09-18
申请人： FUJITSU LIMITED , GET/ENST-Bretagne , KIMURA, Dai , GUILLOUD, Frédéric , PYNDIAH, Ramesh Mahendra
发明人： KIMURA, Dai , GUILLOUD, Frédéric , PYNDIAH, Ramesh Mahendra
IPC分类号： H04L1/00 , H04L1/06
CPC分类号： H04L1/0045 , H03M13/1171 , H04L1/0057 , H04L1/06
摘要： A wireless communication system constructed by a MIMO antenna system and transmitting information from a transmitter having Nt number of transmitting antennas to a receiver 3 having Nr number of receiving antennas. The receiver 3 of this wireless communication system 1 linking the inputs and outputs between a demodulating unit 32 demodulating the input signals from receiving antennas 31 and a decoding unit 35 receiving as input that demodulation output and decoding the non-binary LDPC code of the GF(q) one-to-one under predetermined conditions to enable the inputs and outputs of this demodulating unit 32 and decoding unit 35 to be directly connected and thereby improve the decoding characteristic. That predetermined condition is preferably q=2 Nt.m .
摘要翻译：一种由MIMO天线系统构成的无线通信系统，并将具有N个发送天线的发送机的信息发送到具有N个接收天线数量的接收机3。该无线通信系统1的接收机3在解调来自接收天线31的输入信号的解调单元32和接收作为输入的解码单元35之间的输入和输出之间连接输入和输出，解调输出和解码GF的非二进制LDPC码 q）在预定条件下一对一，使得解调单元32和解码单元35的输入和输出能够直接连接，从而提高解码特性。该预定条件优选为q = 2 Nt.m。

6. 发明申请

WO2017074590A1 DYNAMICALLY SCHEDULING OF NODE PROCESSING DURING ITERATIVE DECODING 审中-公开
标题翻译：迭代译码中节点处理的动态调度
公开(公告)号：WO2017074590A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/051817
申请日：2016-09-15
申请人： SANDISK TECHNOLOGIES LLC
发明人： ACHTENBERG, Stella , SHARON, Eran , ZAMIR, Ran
IPC分类号： H03M13/11 , G06F11/10 , H03M13/15 , H03M13/29 , H03M13/37
CPC分类号： H03M13/3746 , G06F11/10 , G06F11/1072 , G11C29/52 , H03M13/1108 , H03M13/1137 , H03M13/114 , H03M13/116 , H03M13/1171 , H03M13/1191 , H03M13/1515 , H03M13/152 , H03M13/2957 , H03M13/3707 , H03M13/45
摘要： An iterative ECC decoder such as a bit flipping LDPC decoder includes a processor and a scheduler coupled to the processor. The processor is configured to process a set of nodes related to a representation of a codeword during a first decode iteration. The nodes are processed in a first order. The scheduler is configured to generate a schedule that indicates a second order of the set of nodes. The second order is different from the first order.
摘要翻译：诸如位翻转LDPC解码器之类的迭代ECC解码器包括处理器和耦合到处理器的调度器。处理器被配置为在第一解码迭代期间处理与码字的表示相关的一组节点。节点按照第一顺序进行处理。调度器被配置成生成指示该组节点的第二顺序的调度。第二顺序与第一顺序不同。

7. 发明申请

WO2015127757A1 多元码调制映射方法、装置和计算机存储介质审中-公开
公开(公告)号：WO2015127757A1
公开(公告)日：2015-09-03
申请号：PCT/CN2014/083320
申请日：2014-07-30
申请人：中兴通讯股份有限公司
发明人：段灿 , 徐俊 , 许进 , 郁光辉 , 佟宁宁 , 赵旦峰 , 周相超
IPC分类号： H04L27/00
CPC分类号： H04L27/36 , H03M13/1157 , H03M13/1171 , H03M13/255 , H04L1/0041 , H04L1/0058 , H04L1/0066 , H04L1/0071 , H04L1/1893 , H04L27/3405
摘要：本发明公开了一种多元码调制映射方法及装置，涉及通信领域，为提高通信可靠性的而设计。所述方法包括：将包括K个多元码的第一序列进行多元域编码，获得包括N个多元码的第二序列；依据多元域元素数q和调制阶数M计算得到K 1 和K 2 ；其中K 1 *log 2 q=K 2 *log 2 M，且所述K 1 和K 2 均为不小于2的整数，所述q和M均为2的幂次；将所述第二序列以K 1 个多元码为一组，分为z个多元码组；其中，C=式(I)，所述式(II)表示向上取整；将每一个所述多元码组映射到星座图，形成K 2 个M阶调制符号；将z组所述M阶调制符号按顺序级联形成待发送的调制符号。本发明还同时公开了一种计算机存储介质。

8. 发明申请

WO2011085355A1 BELIEF PROPAGATION PROCESSOR 审中-公开
标题翻译： BELIEF传播处理器
公开(公告)号：WO2011085355A1
公开(公告)日：2011-07-14
申请号：PCT/US2011/020794
申请日：2011-01-11
申请人： REYNOLDS, David , VIGODA, Benjamin , ALEXEYEV, Alexander
发明人： REYNOLDS, David , VIGODA, Benjamin , ALEXEYEV, Alexander
IPC分类号： G06K5/04 , G06F11/00
CPC分类号： G06F11/10 , G06F11/1008 , G06G7/122 , G06G7/1942 , H03M13/1102 , H03M13/1111 , H03M13/1171 , H03M13/255 , H03M13/45 , H03M13/6597
摘要： A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.
摘要翻译：处理器包括：第一存储器模块，用于存储每个表示相应输入的第一组存储值;以及第二存储器模块，用于以模拟形式存储第二组存储值。模拟模块耦合到第一和第二存储器模块。模拟模块被配置为在至少一次迭代的每个操作周期中，基于第一和第二组存储值来更新第二组存储值中的至少一些。输出模块用于从第二组存储值中的至少一些产生一组输出。

9. 发明申请

WO2011010180A1 METHOD AND APPARATUS FOR NON-BINARY LOW DENSITY PARTY CHECK CODING 审中-公开
标题翻译：非二进制低密度方检验方法和装置
公开(公告)号：WO2011010180A1
公开(公告)日：2011-01-27
申请号：PCT/IB2009/006321
申请日：2009-07-22
申请人： THOMSON LICENSING , ZHOU, Wei , ZOU, Li
发明人： ZHOU, Wei , ZOU, Li
IPC分类号： H04L25/03 , H04L27/34 , H04L27/38 , H04L1/00 , H03M13/25
CPC分类号： H03M13/1171 , H03M13/255 , H04L1/0057 , H04L1/06 , H04L25/03171 , H04L27/2627 , H04L27/2649 , H04L27/3405 , H04L27/38 , H04L2025/03611
摘要： Methods and apparatus for non-binary, low density parity check coding are disclosed. The inventive methods comprise encoding the signal with a low density parity check code, rotating a component of the coded signal, delaying the rotated component, and interleaving symbols associated with the rotated and delayed components of the signal.
摘要翻译：公开了用于非二进制，低密度奇偶校验编码的方法和装置。本发明的方法包括用低密度奇偶校验码对信号进行编码，旋转编码信号的分量，延迟旋转的分量，以及交织与信号的旋转和延迟分量相关联的符号。

10. 发明申请

WO2010006430A1 DECODING OF LINEAR CODES WITH PARITY CHECK MATRIX 审中-公开
标题翻译：用奇偶校验矩阵解码线性代码
公开(公告)号：WO2010006430A1
公开(公告)日：2010-01-21
申请号：PCT/CA2009/000983
申请日：2009-07-15
申请人： THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY , GROSS, Warren, J. , MANNOR, Shie , SARKIS, Gabi
发明人： THE ROYAL INSTITUTION FOR THE ADVANCEMENT OF LEARNING/MCGILL UNIVERSITY , GROSS, Warren, J. , MANNOR, Shie , SARKIS, Gabi
IPC分类号： H03M13/11 , H04L1/22
CPC分类号： H03M13/1171 , H04L1/0057
摘要： A decoding method and system for stochastic decoding of linear codes with the parity check matrix comprising elements of a Galois field is provided. Each encoded sample of a set of encoded samples is first scaled by a scaling factor proportional to a noise level of the set of encoded samples. Each of the scaled encoded samples is then converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of symbols or bits. Each probability message is then provided to a respective variable node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear code. Using the logic circuitry each probability message is passed through the factor graph by performing for each received symbol at the variable nodes the equality function, at the permutation nodes one of multiplication and division, and at the parity check nodes the parity check function, wherein each of the variable nodes provides an output symbol in dependence upon each received symbol.
摘要翻译：提供了一种具有包括伽罗瓦域元素的奇偶校验矩阵的线性码随机解码的解码方法和系统。一组编码样本的每个编码样本首先按与编码样本集合的噪声电平成比例的缩放因子来缩放。然后将每个经缩放的编码样本转换成相应的概率。对于每个概率，相应的概率消息是通过将每个概率编码为符号或比特的序列而生成的。然后将每个概率消息提供给用于随机解码的逻辑电路的相应可变节点。逻辑电路表示线性码的奇偶校验矩阵的因子图。使用逻辑电路，通过对可变节点处的每个接收到的符号执行相等函数，在置换节点乘法和除法之一以及奇偶校验节点处执行奇偶校验功能，将每个概率消息传递通过因子图，其中每个可变节点根据每个接收的符号提供输出符号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式