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1. 发明申请

WO2009142664A1 CLOCK GENERATION USING A FRACTIONAL PHASE DETECTOR 审中-公开
标题翻译：使用相位相位检测器的时钟生成
公开(公告)号：WO2009142664A1
公开(公告)日：2009-11-26
申请号：PCT/US2008/086781
申请日：2008-12-15
申请人： XILINX, INC.
发明人： NOVELLINI, Paolo , CUCCHI, Silvio , GUASTI, Giovanni
IPC分类号： H03L7/085
CPC分类号： H03L7/1806 , H03L7/091 , H03L7/0994 , H03L2207/50 , H04J3/0691
摘要： Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock signal having a frequency that differs from the frequency of the output clock signal. The frequency of the output clock signal is a product from multiplying the frequency for the input signal and an integer ratio. The circuit includes an accumulator, a fractional phase detector, and a loop filter. The accumulator periodically adds a numerical offset value to a numerical phase value. The output clock signal is generated from this numerical phase value. The fractional phase detector generates from the numerical phase value a respective numerical phase error for each of the transitions of the input signal. The loop filter generates the numerical offset value from a filtering of the respective numerical phase errors.
摘要翻译：提供了从输入信号产生具有减小的偏移的一个或多个输出时钟信号的电路。输入信号具有从具有与输出时钟信号的频率不同的频率的原始时钟信号的转变导出的转变。输出时钟信号的频率是乘以输入信号的频率和整数比。该电路包括一个累加器，一个分数相位检测器和一个环路滤波器。累加器周期性地将数字偏移值添加到数值相位值。从该数值相位值产生输出时钟信号。分数相位检测器从数字相位值生成输入信号的每个转换的相应数值相位误差。环路滤波器从相应的数值相位误差的滤波中产生数字偏移值。

2. 发明申请

WO2016043816A1 LANE-TO-LANE-DE-SKEW FOR TRANSMITTERS 审中-公开
标题翻译：用于变送器的LANE-TO-LANE-DE-SKEW
公开(公告)号：WO2016043816A1
公开(公告)日：2016-03-24
申请号：PCT/US2015/027823
申请日：2015-04-27
申请人： XILINX, INC.
发明人： NOVELLINI, Paolo , GUASTI, Giovanni
IPC分类号： G06F13/40 , G06F13/42
CPC分类号： H04B1/0475 , G06F1/10 , G06F5/06 , G06F13/4018 , G06F13/423 , G11C7/22 , G11C7/222 , H04L25/05
摘要： In a method relating generally to starting a plurality of transmitters (190), a sequence is initiated for each of the plurality of transmitters (190) having corresponding data buffers (121). Latency is set for each of the data buffers (121) responsive to execution of the sequence. The sequence includes: obtaining a read address (108) associated with a read clock signal (106) (501); obtaining a write address (109) associated with a write clock signal (105) (502); determining a difference between the read address (108) and the write address (109) (503); asserting a flag signal (113) associated with the difference (111) (504); and adjusting the read clock signal (106) to change the difference (111) to locate a change of state location for the flag signal (113) to set the latency for a data buffer (121) of the data buffers (121) (505).
摘要翻译：在一般涉及启动多个发射机（190）的方法中，针对具有对应的数据缓冲器（121）的多个发射机（190）中的每一个启动序列。响应于序列的执行，为每个数据缓冲器（121）设置延迟。该序列包括：获得与读取时钟信号（106）相关联的读取地址（108）（501）; 获得与写入时钟信号（105）相关联的写入地址（109）（502）; 确定读取地址（108）和写入地址（109）（503）之间的差异; 断言与差值（111）相关联的标志信号（113）（504）; 以及调整所述读取时钟信号（106）以改变所述差异（111）以定位所述标志信号（113）的状态位置的改变，以设置数据缓冲器（121）的数据缓冲器（121）的等待时间（505））。

3. 发明申请

WO2015065543A1 SERDES RECEIVER OVERSAMPLING RATE 审中-公开
标题翻译： SERDES接收器超频率
公开(公告)号：WO2015065543A1
公开(公告)日：2015-05-07
申请号：PCT/US2014/046020
申请日：2014-07-09
申请人： XILINX, INC.
发明人： NOVELLINI, Paolo , TORZA, Anthony
IPC分类号： G11C19/00 , H03M9/00
CPC分类号： G06F13/4282 , H03M9/00 , H04J3/0685 , H04L25/14
摘要： An apparatus relates generally to serializer-deserializers. In such an apparatus, a first serializer-deserializer (210) has a first data path (251) and a data eye path (252). The first data path is coupled to a first data out interface (241) of the first serializer-deserializer. A second serializer-deserializer (211) has a second data path (261). The second data path is coupled to a second data out interface (242) of the second serializer-deserializer. The data eye path of the first serializer-deserializer is coupled (220, 230) to the second data path of the second serializer-deserializer. Related methods are also described.
摘要翻译：一种装置一般涉及串行器 - 解串器。在这种装置中，第一串行器 - 解串器（210）具有第一数据路径（251）和数据眼路径（252）。第一数据路径耦合到第一串行器 - 解串器的第一数据输出接口（241）。第二串行器 - 解串器（211）具有第二数据路径（261）。第二数据路径耦合到第二串行器 - 解串器的第二数据输出接口（242）。第一串行器 - 解串器的数据眼路径耦合（220,230）到第二串行器 - 解串器的第二数据路径。还描述了相关方法。

4. 发明申请

WO2022139891A1 A CIRCUIT FOR AND METHOD OF PROCESSING A DATA STREAM 审中-公开
公开(公告)号：WO2022139891A1
公开(公告)日：2022-06-30
申请号：PCT/US2021/048766
申请日：2021-09-01
申请人： XILINX, INC.
发明人： NOVELLINI, Paolo
IPC分类号： H04L7/00 , H03L7/091
摘要： A circuit for processing a data stream is described. The circuit comprises a burst phase detector configured to receive a data input signal; a clocking circuit coupled to the burst phase detector, wherein the clocking circuit is configured to receive a delayed data input signal and to receive a data stream phase signal and a data stream detect signal; and a programmable clock generator configured to receive a plurality of clock signals; wherein a selected clock signal of the plurality of clock signals is generated by the programmable clock generator and provided to the burst phase detector and the clocking circuit.

5. 发明申请

WO2021002988A1 LOW LATENCY RECEIVER 审中-公开
公开(公告)号：WO2021002988A1
公开(公告)日：2021-01-07
申请号：PCT/US2020/035570
申请日：2020-06-01
申请人： XILINX, INC.
发明人： NOVELLINI, Paolo , TAYLOR, David F. , RICHARDSON, Alastair J.
IPC分类号： G06F13/38 , G06F13/42 , H03L7/08
摘要： A device includes a physical medium attachment (PMA) (110), a physical coding sublayer (PCS) (120), a phase detector (140), and an oscillator (150). The PMA (110) receives data (102) at a first speed and overclocks the received data to a second speed (112), wherein the second speed is higher than the first speed. The PCS (120) receives the data (112) at the second speed. The phase detector (140) receives another data (122) from the PCS (120) wherein the another data (122) is based on the received data at the second speed (112) or the phase detector (140) is configured to receive the data at the second speed (112) from the PMA (110). The phase detector (140) adjusts a phase based on bit transitions. The oscillator (150) is coupled to the phase detector (140) and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector (150). The oscillator (150) clocks the PMA (110) based on the adjusted clock.

6. 发明申请

WO2013180766A1 DISTORTION TOLERANT CLOCK AND DATA RECOVERY SYSTEM 审中-公开
标题翻译：失败容忍时钟和数据恢复系统
公开(公告)号：WO2013180766A1
公开(公告)日：2013-12-05
申请号：PCT/US2013/023926
申请日：2013-01-30
申请人： XILINX INC.
发明人： GUASTI, Giovanni , NOVELLINI, Paolo
IPC分类号： H03L7/08 , H03L7/091 , H04L7/033
CPC分类号： H03L7/0807 , H03L7/091 , H04L7/0331
摘要： A system can include a phase detector (105) configured to generate a phase error signal indicating a phase error of an input signal compared to an output signal and a first filter (110) coupled to the phase detector and configured to generate a first control signal derived from the phase error signal. The system can include a pattern error detector (120) configured to generate a pattern error signal specifying a pattern error of the input signal compared to the output signal and a second filter (125) coupled to the pattern error detector and configured to generate a second control signal derived from the pattern error signal. The system further can include a controlled oscillator (115) coupled to the first filter and the second filter, wherein the controlled oscillator is configured to generate the output signal responsive to the first control signal, the second control signal, and a center frequency signal.
摘要翻译：系统可以包括相位检测器（105），其被配置为产生相对于输出信号指示输入信号的相位误差的相位误差信号和耦合到相位检测器的第一滤波器（110），并且被配置为产生第一控制信号来自相位误差信号。该系统可以包括模式误差检测器（120），其被配置为产生与输出信号相比指定输入信号的模式误差的模式误差信号，以及耦合到模式误差检测器的第二滤波器（125），并且被配置为产生第二从模式误差信号导出的控制信号。该系统还可以包括耦合到第一滤波器和第二滤波器的受控振荡器（115），其中受控振荡器被配置为响应于第一控制信号，第二控制信号和中心频率信号产生输出信号。

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