专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2015177592A1 PROGRAMMING APPARATUS AND METHOD FOR REPAIRING CACHE ARRAYS IN MULTI-CORE MICROPROCESSOR 审中-公开
标题翻译：用于修复多核微处理器中的高速缓存阵列的编程设备和方法
公开(公告)号：WO2015177592A1
公开(公告)日：2015-11-26
申请号：PCT/IB2014/003185
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HENRY, G., Glenn , JAIN, Dinesh, K. , GASKINS, Stephan
IPC分类号： G06F15/163
CPC分类号： G06F12/0893 , G06F1/3275 , G06F8/66 , G06F9/4403 , G06F12/0811 , G06F12/12 , G06F15/177 , G06F2212/222 , G06F2212/283 , G06F2212/601 , G11C7/20 , G11C17/16 , G11C17/18 , G11C2029/4402
摘要： An apparatus includes a programmer, a stores, and a plurality of cores. The programmer programs a fuse array with compressed configuration data. The stores provides for storage and access of decompressed configuration data sets. Each of a plurality of cores is coupled to the fuse array. One of the cores is accesses the fuse array upon power-up/reset to decompress and store decompressed configuration data sets for one or more cache memories. Each of the cores includes reset logic and sleep logic. The reset logic employs the decompressed configuration data sets to initialize the one or more cache memories upon power- up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.
摘要翻译：一种装置包括编程器，存储器和多个核心。编程器编程具有压缩配置数据的保险丝阵列。这些商店提供解压缩配置数据集的存储和访问。多个芯中的每一个耦合到熔丝阵列。其中一个内核在上电/复位时访问熔丝阵列，以解压缩并存储一个或多个缓存存储器的解压缩配置数据集。每个核心包括复位逻辑和睡眠逻辑。复位逻辑采用解压缩的配置数据集在上电/复位时初始化一个或多个高速缓冲存储器。休眠逻辑确定在电源门控事件之后恢复电力，随后访问商店以检索并使用解压缩的配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

2. 发明申请

WO2015177596A1 MULTI-CORE MICROPROCESSOR POWER GATING CACHE RESTORAL PROGRAMMING MECHANISM 审中-公开
标题翻译：多核心微处理器功率增益缓存缓存编程机制
公开(公告)号：WO2015177596A1
公开(公告)日：2015-11-26
申请号：PCT/IB2014/003267
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HENRY, G., Glenn , JAIN, Dinesh, K. , GASKINS, Stephan
IPC分类号： G11C15/04
CPC分类号： G06F12/0893 , G06F1/3275 , G06F8/66 , G06F9/4403 , G06F12/0811 , G06F12/12 , G06F15/177 , G06F2212/222 , G06F2212/283 , G06F2212/601 , G11C7/20 , G11C17/16 , G11C17/18 , G11C2029/4402
摘要： An apparatus includes a device programmer and a stores. The device programmer programs a semiconductor fuse array with compressed configuration data for a plurality of cores disposed on a die. The stores includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores is configured to access the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub- stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches.
摘要翻译：一种装置包括装置编程器和商店。器件编程器针对设置在管芯上的多个核心编程具有压缩配置数据的半导体熔丝阵列。存储器包括多个子存储器，每个子存储器对应于多个核心中的每一个，其中多个核心中的一个核心被配置为在上电/复位时访问半导体熔丝阵列以读取和解压缩压缩的配置数据，并且存储多个子存储器中的多个核心内的一个或多个高速缓存存储器的多个解压缩配置数据集，并且其中，在电源门控事件之后，所述多个核心中的每一个之一随后访问多个子存储中的每个子存储器中的相应一个，以检索和使用解压缩的配置数据集来初始化一个或多个高速缓存。

3. 发明申请

WO2015177595A1 MULTI-CORE PROGRAMMING APPARATUS AND METHOD FOR RESTORING DATA ARRAYS FOLLOWING A POWER GATING EVENT 审中-公开
标题翻译：多核编程设备和恢复功率增益事件数据阵列的方法
公开(公告)号：WO2015177595A1
公开(公告)日：2015-11-26
申请号：PCT/IB2014/003259
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： GLENN, Henry, G. , JAIN, Dinesh, K. , GASKINS, Stephan
IPC分类号： G11C17/00
CPC分类号： G06F12/0893 , G06F1/3275 , G06F8/66 , G06F9/4403 , G06F12/0811 , G06F12/12 , G06F15/177 , G06F2212/222 , G06F2212/283 , G06F2212/601 , G11C7/20 , G11C17/16 , G11C17/18 , G11C2029/4402
摘要： An apparatus includes a device programmer and a plurality of cores. The programmer programs a semiconductor fuse array with compressed configuration data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and stores decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.
摘要翻译：一种装置包括装置编程器和多个核。编程器对具有压缩配置数据的半导体熔丝阵列进行编程。多个核心中的每个核心在加电/复位时访问熔丝阵列以读取和解压缩压缩数据，并且将存储器中的一个或多个高速缓冲存储器的解压缩数据集存储在多个核心的每一个中，该存储器耦合到多个核心中的每一个。多个核心中的每一个具有复位逻辑和睡眠逻辑。复位逻辑采用解压缩数据集在上电/复位时初始化一个或多个高速缓存存储器。休眠逻辑确定在电源门控事件之后恢复电力，并且随后访问商店以检索和使用解压缩数据集来初始化电源门控事件之后的一个或多个高速缓存。

4. 发明申请

WO2016042354A1 CACHE MEMORY DIAGNOSTIC WRITEBACK 审中-公开
标题翻译：缓存记忆诊断写
公开(公告)号：WO2016042354A1
公开(公告)日：2016-03-24
申请号：PCT/IB2014/003103
申请日：2014-11-26
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HOOKER, Rodney, E. , GASKINS, Stephan , REED, Douglas, R. , CHEN, Jason
IPC分类号： G06F12/08
CPC分类号： G11C29/38 , G06F12/0804 , G06F12/0811 , G06F12/0833 , G06F12/084 , G06F12/0842 , G06F12/0857 , G06F12/0864 , G06F2212/1024 , G06F2212/6042 , G11C29/44
摘要： A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the cache line. The cache memory includes an engine comprising one or more finite state machines. The processor also includes an interface to a bus over which the processor writes back modified cache lines from the cache memory to the system memory in response to encountering an architectural writeback and invalidate instruction. The processor also invalidates the state of the entries of the cache memory in response to encountering the architectural writeback and invalidate instruction. In response to being instructed to perform a cache diagnostic operation, for each entry of the entries, the engine writes the state and the tag of the entry on the bus and does not invalidate the state of the entry.
摘要翻译：处理器包括具有多个条目的高速缓冲存储器。每个条目保存高速缓存行的数据，高速缓存行的状态和高速缓存行的标签。高速缓存存储器包括包括一个或多个有限状态机的引擎。处理器还包括到总线的接口，响应于遇到架构回写和无效指令，处理器将经修改的高速缓存线从高速缓冲存储器写回系统存储器。响应于遇到架构回写和无效指令，处理器也使高速缓冲存储器条目的状态无效。响应于被指示执行高速缓存诊断操作，对于条目的每个条目，引擎将条目的状态和标签写入总线，并且不使条目的状态无效。

5. 发明申请

WO2015177593A1 MULTI-CORE DATA ARRAY POWER GATING CACHE RESTORAL PROGRAMMING MECHANISM 审中-公开
标题翻译：多核心数据阵列功率调节缓存编程机制
公开(公告)号：WO2015177593A1
公开(公告)日：2015-11-26
申请号：PCT/IB2014/003198
申请日：2014-12-12
申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
发明人： HENRY, G., Glenn , JAIN, Dinesh, K. , GASKINS, Stephan
IPC分类号： G11C17/18 , G11C29/00
CPC分类号： G06F12/0893 , G06F1/3275 , G06F8/66 , G06F9/4403 , G06F12/0811 , G06F12/12 , G06F15/177 , G06F2212/222 , G06F2212/283 , G06F2212/601 , G11C7/20 , G11C17/16 , G11C17/18 , G11C2029/4402
摘要： An apparatus including a device programmer (310), a stores (1130), and a plurality of cores (332; 1101). The device programmer (310) programs a semiconductor fuse array (336) with compressed configuration data for a plurality of cores (332; 1101) disposed on a die (330). The stores (1130) has a plurality of sub-stores (1131; 1132; 1133; 1134) that each correspond to each of the plurality of cores (1101), where one of the plurality of cores (1101) is configured to access the semiconductor fuse array (336) upon power- up/reset to read and decompress the configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories (1102) within the each of the plurality of cores (1101) in the plurality of sub-stores (1131; 1132; 1133; 1134). The plurality of cores each has sleep logic (1106) that is configured to subsequently access a corresponding one of the each of the plurality of sub-stores (1131; 1132; 1133; 1134) to retrieve and employ the decompressed configuration data sets to initialize the one or more caches (1102) following a power gating event.
摘要翻译：一种包括设备编程器（310），存储器（1130）和多个核心（332; 1101）的设备。器件编程器（310）用设置在管芯（330）上的多个芯（332; 1101）的压缩配置数据来编程半导体熔丝阵列（336）。存储器（1130）具有多个子存储器（1131; 1132; 1133; 1134），每个子存储器对应于多个核心（1101）中的每一个，多个核心（1101）中的一个被配置为访问在上电/复位时，半导体熔丝阵列（336）读取和解压缩配置数据，并且存储多个解压缩的配置数据集，用于在多个核心（1101）内的每一个内部的一个或多个高速缓冲存储器（1102）在多个子商店中（1131; 1132; 1133; 1134）。多个核心各具有休眠逻辑（1106），其被配置为随后访问多个子存储（1131; 1132; 1133; 1134）中的每一个子对象的对应的一个，以检索和使用解压缩的配置数据集来初始化在电源门控事件之后的一个或多个高速缓存（1102）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式