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1. 发明申请

WO2006007619A3 DECENTRALISED FAULT-TOLERANT CLOCK PULSE GENERATION IN VLSI CHIPS 审中-公开
标题翻译： VLSI CHIPS中分散容错时钟产生
公开(公告)号：WO2006007619A3
公开(公告)日：2006-05-04
申请号：PCT/AT2005000280
申请日：2005-07-18
申请人： UNIV WIEN TECH , SCHMID ULRICH , STEININGER ANDREAS
发明人： SCHMID ULRICH , STEININGER ANDREAS
IPC分类号： G06F11/16
CPC分类号： G06F11/1604 , G06F1/04
摘要： The invention relates to method for the distributed fault-tolerant clock pulse generation in hardware systems, especially in VLSI chips, systems-on-a-chip, IP-cores and PCBs, said method being characterised in that a) the system clock pulse is formed in a distributed manner by means of a plurality of intercommunicating, fault-tolerant clock pulse synchronisation algorithms (TS-Algs), without using external or internal clock pulse oscillators, by i) any number of such TS-Algs exchanging information between each other by means of a network (TS-Net) subjected to any permanent and transient errors, ii) each TS-Alg is associated with at least one functional unit (Fu1, Fu2, ), generating the local clock pulse thereof; b) all local clock pulses are maintained with a guaranteed frequency synchronisation, c) a specified number of transient and/or permanent errors can occur in the TS-Algs or in the TS-Net without affecting the clock pulse generation and/or the synchronisation accuracy; and d) the system clock pulse automatically reaches the maximum possible frequency determined by the used production technology, the Placement & Routing of the TS-Algs and the TS-Nets, and the current operating conditions (temperature, supply voltage etc.).
摘要翻译：本发明涉及硬件系统中的分布式容错时钟生成方法，特别是VLSI芯片，片上系统，IP核和PCB，其特征在于a。系统时钟由通过i分配而不使用外部或内部时钟振荡器的多个互相通信容错时钟同步算法（TS-Algs）形成。任何数量的这种TS-Algs通过任意的，永久的和容易发生瞬态错误的网络（TS-Net）通过时钟信号彼此交换信息，ii。每个TS Alg与其产生本地时钟的一个或多个功能单元（Fu1，Fu2，...）相关联，b。所有的本地时钟频率同步的保证被保持，一个在这个意义上，在任意的时间间隔至多通过一个给定的恒定数量的时钟周期的不同而不同，任意两个本地时钟信号，以使从由合适的时钟转换电路（分路器等）的下游连接的任何本地时钟可以导出全局系统时钟，这允许芯片上任何功能单元的全局同步通信，c。在TS-Algs或TS-Net中可能发生指定数量的瞬态和/或永久性错误，而不会影响时钟生成和/或同步精度，d。系统时钟自动达到由所使用的制造技术，TS和TS ALGS篮网的布局和布线，并且当前的操作条件（温度，电源电压等）决定的最大频率。

2. 发明申请

WO2006015955A3 METHOD FOR REGISTERING ERRORS AND CORRESPONDING REGISTER 审中-公开
标题翻译：方法错误注册及相应的寄存器
公开(公告)号：WO2006015955A3
公开(公告)日：2006-06-08
申请号：PCT/EP2005053730
申请日：2005-08-01
申请人： BOSCH GMBH ROBERT , KOTTKE THOMAS , STEININGER ANDREAS , EL SALLOUM CHRISTIAN
发明人： KOTTKE THOMAS , STEININGER ANDREAS , EL SALLOUM CHRISTIAN
IPC分类号： G06F11/07
CPC分类号： G06F11/1679 , G06F11/0739 , G06F11/0772 , G06F11/0793 , G06F11/0796 , G06F2201/845
摘要： The invention relates to a method for registering errors and to a register which is associated with a dual calculating system. Information in the form of bits is stored in the register and the dual calculating system contains an error recognising mechanism, whereby the bits in the register represent at least one error signal of the error recognition mechanism as an error bit.
摘要翻译：一种用于错误注册方法和注册其与双处理器系统，其中，存储在比特的形式，其中所述的双处理器系统包括一个错误检测机制寄存器信息相关联，其中表示错误检测机构的在寄存器中的至少错误比特的误差信号的位。

3. 发明申请

WO2005045664A2 METHOD AND DEVICE FOR SWITCHING BETWEEN AT LEAST TWO OPERATING MODES OF A PROCESSOR UNIT 审中-公开
标题翻译：方法和设备之间切换处理器单元的至少两种工作模式
公开(公告)号：WO2005045664A2
公开(公告)日：2005-05-19
申请号：PCT/DE2004001859
申请日：2004-08-20
申请人： BOSCH GMBH ROBERT , WEIBERLE REINHARD , KOTTKE THOMAS , STEININGER ANDREAS
发明人： WEIBERLE REINHARD , KOTTKE THOMAS , STEININGER ANDREAS
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/48
CPC分类号： G06F9/30181 , G06F9/30076 , G06F9/30189 , G06F9/3885 , G06F2201/845
摘要： The invention relates to a method and a device for switching between at least two operating modes (SM, LM) of a processor unit (100, 101) comprising at least two execution units (ALUA, ALUB) for running programs (P1, P2, P3). At least one characteristic (K2) associated with at least the programs (P1, P2, P3) differentiates between the at least two operating modes (SM, LM), and switching between the operating modes is carried out according to the characteristic (K1-K4, KB) such that the processor unit (100, 101) runs the programs (P1, P2, P3) according to the associated operating mode.
摘要翻译：为具有用于执行程序（P1，P2，P3）至少两个执行单元（ALUA，ALUB）的处理器单元（100，101）中的至少两种操作模式（SM，LM），至少所述程序（P1，P2之间的切换的方法和装置，P3）至少分配标识符（K2），它允许区分（其中至少两个操作模式之间操作SM，LM），以及切换作为标识符（K1-K4，KB）的功能发生时，使得该处理器单元（100，101）处理根据操作的分配模式的程序（P1，P2，P3）。

4. 发明申请

WO2006015964A3 METHOD FOR DELAYING ACCESS TO DATA AND/OR COMMANDS OF A DUAL COMPUTER SYSTEM, AND CORRESPONDING DELAYING UNIT 审中-公开
标题翻译：方法DEFER访问数据和/或两个计算机系统的命令和相关延迟单元
公开(公告)号：WO2006015964A3
公开(公告)日：2006-05-11
申请号：PCT/EP2005053791
申请日：2005-08-03
申请人： BOSCH GMBH ROBERT , MUELLER BERND , HARTER WERNER , KOTTKE THOMAS , STEININGER ANDREAS
发明人： MUELLER BERND , HARTER WERNER , KOTTKE THOMAS , STEININGER ANDREAS
IPC分类号： G06F11/16
CPC分类号： G06F11/1641 , G06F11/1679 , G06F11/1695 , G06F2201/845
摘要： Disclosed are a delaying unit (102) and a method for delaying access to data and/or commands of a dual computer system comprising a first (100) and a second computer (101), the first computer operating in a time-deferred manner relative to the second computer. The delaying unit is configured such that the deferral in the dual computer system is compensated in at least one of the two computers when data and/or commands are accessed. Also disclosed are a method and a delaying unit for delaying access to data and/or commands of a computer system comprising error detection mechanisms. Said method and delaying unit are characterized in that the time lapsing between undelayed access to data and/or commands and the detection of an error is compensated.
摘要翻译：延迟单元（102）和方法，用于延迟所述访问数据和/或双重计算机系统，包括第一（100）和第二计算机（101），其中，所述第一部分相对于第二计算机有一个时间差和延迟单元进行操作的命令被适配这个时间延迟在访问数据在两主机系统补偿和/或命令，以及方法和延迟单元来延迟对数据的访问和/或计算机系统以用于检错的错误检测机制的命令，其特征在于一个非延迟访问之间的持续时间的数据和 /或指令，和检错被补偿。

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