专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2011156038A3 A SUB-THRESHOLD FPGA AND RELATED CIRCUITS AND METHODS THEREOF 审中-公开
标题翻译：子阈值FPGA及其相关电路及其方法
公开(公告)号：WO2011156038A3
公开(公告)日：2012-01-26
申请号：PCT/US2011028805
申请日：2011-03-17
申请人： UNIV VIRGINIA PATENT FOUND , CALHOUN BENTON H , RYAN JOSEPH F
发明人： CALHOUN BENTON H , RYAN JOSEPH F
IPC分类号： H03K19/00
CPC分类号： H03K19/17744 , H03K19/17784 , H03K19/17788
摘要： A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.
摘要翻译：子VT FPGA采用低摆幅双VDD互连方案，以降低每个LUT的FPGA面积，以恒定能量延迟，而在低电压下相对于传统设计，能够以恒定的延迟。这些改进可以通过定制的异步感测放大器，用于存储器单元的分离电压以及改进的通道互连来实现，以优化具有低能量开销的路由延迟。该子阈值FPGA设计可为各种ULP应用提供高能效且具有成本效益的可配置逻辑。

2. 发明申请

WO2012012538A3 SRAM CELL 审中-公开
公开(公告)号：WO2012012538A3
公开(公告)日：2014-03-27
申请号：PCT/US2011044691
申请日：2011-07-20
申请人： UNIV VIRGINIA PATENT FOUND , CALHOUN BENTON H , MANN RANDY W
发明人： CALHOUN BENTON H , MANN RANDY W
IPC分类号： G11C17/00
CPC分类号： H01L27/1104 , G11C11/412 , H01L21/28035 , H01L21/28088 , H01L21/28097 , H01L21/768 , Y10S257/903
摘要： Systems and methods of forming memory cells are described including memory cell topologies with cross-coupled inverters including substantially unidirectional gate conductors. Gate conductors for access transistors may also be provided that are substantially aligned with a long axis of the inverter gate conductor. Additionally, contacts of one inverter in a cross-coupled pair may be disposed substantially aligned with a long axis of the other inverter's gate conductor. Thus, the inverter gate conductors, access transistor gate conductors, and contacts may be formed substantially unidirectionally. Separately formed rectangular active regions may also be disposed orthogonal to the gate conductors across pull up, pull down and access transistors. The separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with and narrower than, an active region associated with a pull down transistor of the inverter. Thus, 6T SRAM, and similar, memory cell topologies may be provided in which the major components are formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing the gate conductors of the inverters and access transistors.
摘要翻译：描述形成存储器单元的系统和方法包括具有包括基本上单向栅极导体的交叉耦合反相器的存储单元拓扑。还可以提供用于存取晶体管的栅极导体，其基本上与逆变器栅极导体的长轴对准。此外，交叉耦合对中的一个逆变器的触点可以布置成与另一个逆变器的栅极导体的长轴基本对准。因此，逆变器栅极导体，存取晶体管栅极导体和触点可以基本上单向地形成。单独形成的矩形有源区也可以跨越上拉，下拉和接入晶体管而与栅极导体正交设置。可以形成分离的有源区，使得与存取晶体管和/或上拉晶体管相关联的有源区域与与反相器的下拉晶体管相关联的有源区域不连续并且比其窄。因此，可以提供6T SRAM和类似的存储单元拓扑结构，其中主要部件基本上由矩形线阵列形成，包括单向栅极导体和触点，以及与逆变器的栅极导体和通路的单向矩形有源区晶体管。

3. 发明申请

WO2014152967A2 METHODS AND APPARATUS FOR A SINGLE INDUCTOR MULTIPLE OUTPUT (SIMO) DC-DC CONVERTER CIRCUIT 审中-公开
标题翻译：单电感多输出（SIMO）DC-DC转换器电路的方法和装置
公开(公告)号：WO2014152967A2
公开(公告)日：2014-09-25
申请号：PCT/US2014028442
申请日：2014-03-14
申请人： CALHOUN BENTON H , SHRIVASTAVA AATMESH
发明人： CALHOUN BENTON H , SHRIVASTAVA AATMESH
IPC分类号： H02M3/158 , H02M1/00
CPC分类号： H02M3/158 , H02M2001/009 , Y10T307/406
摘要： In some embodiments, an apparatus includes a single-inductor multiple-output (SIMO) direct current (DC-DC) converter circuit, with the SIMO DC-DC converter circuit having a set of output nodes. The apparatus also includes a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit, where the PDVS circuit has a set of operational blocks with each operational block from the set of operational blocks drawing power from one supply voltage rail from a set of supply voltage rails. Additionally, each output node from the set of output nodes is uniquely associated with a supply voltage rail from the set of supply voltage rails.
摘要翻译：在一些实施例中，一种装置包括单电感多输出（SIMO）直流（DC-DC）转换器电路，其中SIMO DC-DC转换器电路具有一组输出节点。该装置还包括可操作地耦合到SIMO DC-DC转换器电路的全景动态电压缩放（PDVS）电路，其中PDVS电路具有一组操作块，每个操作块与来自一个电源电压的功率块组合轨从一组供电电压轨。此外，来自该组输出节点的每个输出节点与来自该组电源电压轨的电源电压轨迹唯一地相关联。

4. 发明申请

WO2014036451A3 ULTRA LOW POWER SENSING PLATFORM WITH MULTIMODAL RADIOS 审中-公开
标题翻译：超低功率感应平台与多模式无线电
公开(公告)号：WO2014036451A3
公开(公告)日：2015-07-16
申请号：PCT/US2013057597
申请日：2013-08-30
申请人： UNIV VIRGINIA PATENT FOUND , UNIV MICHIGAN
发明人： CALHOUN BENTON H , SHAKHSHEER YOUSEF , ZHANG YANQING , KLINEFELTER ALICIA , WENTZLOFF DAVID D , ROBERTS NATHAN E , OH SEUNGHYUN
IPC分类号： G06F17/50
CPC分类号： H04B1/406 , H04B1/1607 , H04W4/005 , Y02D70/00 , Y02D70/40
摘要： An apparatus comprises a system on a chip (SoC). In some embodiments, the SoC includes a power supply circuit, a power management circuit operatively coupled to the power supply circuit, a first wireless communications circuit and a second wireless communications circuit. The first wireless communications circuit is configured to receive an RF signal and is operatively coupled to the power supply circuit and the power management circuit. The first wireless communications circuit has a net radio frequency (RF) power gain no more than unity before at least one of downconversion of the RF signal or detection of the RF signal. The second wireless communications circuit is operatively coupled to the power supply circuit and the power management circuit.
摘要翻译：一种装置包括芯片上的系统（SoC）。在一些实施例中，SoC包括电源电路，可操作地耦合到电源电路的电源管理电路，第一无线通信电路和第二无线通信电路。第一无线通信电路被配置为接收RF信号并且可操作地耦合到电源电路和电源管理电路。第一无线通信电路在RF信号的下变频或RF信号的检测中的至少一个之前具有不大于1的净射频（RF）功率增益。第二无线通信电路可操作地耦合到电源电路和电源管理电路。

5. 发明申请

WO2014039817A2 LOW POWER CLOCK SOURCE 审中-公开
标题翻译：低功耗时钟源
公开(公告)号：WO2014039817A2
公开(公告)日：2014-03-13
申请号：PCT/US2013058502
申请日：2013-09-06
申请人： CALHOUN BENTON H , SHRIVASTAVA AATMESH
发明人： CALHOUN BENTON H , SHRIVASTAVA AATMESH
IPC分类号： G06F1/04
CPC分类号： H03L1/026 , G06F1/04 , G06F1/324 , G06F1/3287 , G06F1/3296 , H03B5/32 , H03K3/011 , H03K3/0315 , H03L1/02 , H03L1/021 , H03L1/022
摘要： An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.
摘要翻译：超低功耗时钟源包括一个补偿振荡器和一个由比较器电路耦合的未补偿振荡器。在一个示例中，相对于温度，电压，年龄或其他环境参数中的一个或多个中的变化，补偿振荡器比未补偿振荡器更稳定。未补偿的振荡器包括被配置为调整未补偿的振荡器的操作特性的配置输入。在一个示例中，使用来自比较器电路的信息关于来自补偿振荡器和未补偿振荡器的输出信号的比较来调整未补偿振荡器。

6. 发明申请

WO2013123359A2 ENERGY HARVESTING AND CONTROL FOR SENSOR NODE 审中-公开
标题翻译：传感器节能的能量采集和控制
公开(公告)号：WO2013123359A2
公开(公告)日：2013-08-22
申请号：PCT/US2013026390
申请日：2013-02-15
申请人： CALHOUN BENTON H , OTIS BRIAN
发明人： CALHOUN BENTON H , OTIS BRIAN
IPC分类号： A61B5/0478
CPC分类号： H02J50/12 , A61B5/04004 , A61B5/0402 , A61B5/0476 , A61B5/0488 , A61B2560/0214 , A61B2560/0219 , A61N1/3785 , A61N1/3787 , G05F1/613 , G06F1/3287 , H02J17/00 , H02J50/00 , Y02D10/171
摘要： An integrated circuit, such as included as a portion of a sensor node, can include a regulator circuit having an input coupleable to an energy harvesting transducer. The integrated circuit can include a wireless receiver circuit coupled to the regulator circuit and configured to wirelessly receive at least enough operating energy to establish operation of the sensor node without requiring the energy harvesting transducer. The integrated circuit can include a digital processor circuit coupled to the regulator circuit and a power management processor circuit. The digital processor circuit or one or more other circuits can include a subthreshold operational mode established by the power management processor circuit based on the selected energy consumption level. For example, establishing the subthreshold operational mode can include adjusting or selecting a supply voltage so as to establish subthreshold operation of a field effect transistor (FET) in the digital processor circuit or other circuits.
摘要翻译：诸如被包括为传感器节点的一部分的集成电路可以包括具有可耦合到能量收集传感器的输入的调节器电路。集成电路可以包括耦合到调节器电路并被配置为无线地接收至少足够的操作能量以建立传感器节点的操作而无需能量采集传感器的无线接收器电路。集成电路可以包括耦合到调节器电路的数字处理器电路和电源管理处理器电路。数字处理器电路或一个或多个其它电路可以包括由电源管理处理器电路基于所选择的能量消耗水平建立的亚阈值操作模式。例如，建立亚阈值操作模式可以包括调整或选择供电电压，以便在数字处理器电路或其它电路中建立场效应晶体管（FET）的亚阈值操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式