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1. 发明申请

WO2002093404A2 COMPUTING SYSTEM 审中-公开
标题翻译：计算系统
公开(公告)号：WO2002093404A2
公开(公告)日：2002-11-21
申请号：PCT/JP2002/004461
申请日：2002-05-08
申请人： TOKYO ELECTRON DEVICE LIMITED , NISHIHARA, Akinori , HASEBE, Tetsuya , HAYASHI, Hiroaki , MITA, Takashi
发明人： NISHIHARA, Akinori , HASEBE, Tetsuya , HAYASHI, Hiroaki , MITA, Takashi
IPC分类号： G06F15/78
CPC分类号： G06F15/7867
摘要： A computing unit (42) executes a second computing in the middle of a first computing. At this time, the hardware structure of the computing unit (43) is switched in accordance with a computing which is a target of execution. A controller (46) stores the internal state of the computing unit (42) in a memory (44) when a computing to the second computing. And the controller (46) controls execution of the first computing to be continued by returning the internal state stored in the memory (44) to the computing unit (42), when a computing to be executed by the computing unit (42) returns from the second computing to the first computing.
摘要翻译：计算单元（42）在第一计算的中间执行第二计算。此时，根据作为执行对象的计算来切换计算单元（43）的硬件结构。当计算到第二计算时，控制器（46）将计算单元（42）的内部状态存储在存储器（44）中。并且当计算单元（42）执行的计算返回时，控制器（46）通过将存储在存储器（44）中的内部状态返回到计算单元（42）来控制要继续的第一计算的执行，第二次计算到第一次计算。

2. 发明申请

WO2003058429A3 LOGIC COMPUTING SYSTEM AND METHOD 审中-公开
公开(公告)号：WO2003058429A3
公开(公告)日：2003-07-17
申请号：PCT/JP2002/013442
申请日：2002-12-24
申请人： TOKYO ELECTRON DEVICE LIMITED , MITA, Takashi , NISHIHARA, Akinori
发明人： MITA, Takashi , NISHIHARA, Akinori
IPC分类号： G06F15/78 , G06F9/38 , H03K19/177 , G06F17/50
摘要： A FPGA data module to be referred to as a LUT by a logic block (43) is divided into a plurality of modules. Each of a plurality of data registers (41a to 4Id) stores one of the plurality of FPGA data modules. By referring to the FPGA data module(s) stored in one or more of the plurality of data registers (41a to 4Id), a gate circuit (43a) and flip flop (43b) of the logic block (43) generates a logical function value of logic input data. The logical function value of the logic input data is provided as logic output data.

3. 发明申请

WO2002093404A3 COMPUTING SYSTEM 审中-公开
公开(公告)号：WO2002093404A3
公开(公告)日：2002-11-21
申请号：PCT/JP2002/004461
申请日：2002-05-08
申请人： TOKYO ELECTRON DEVICE LIMITED , NISHIHARA, Akinori , HASEBE, Tetsuya , HAYASHI, Hiroaki , MITA, Takashi
发明人： NISHIHARA, Akinori , HASEBE, Tetsuya , HAYASHI, Hiroaki , MITA, Takashi
IPC分类号： G06F15/78
摘要： A computing unit (42) executes a second computing in the middle of a first computing. At this time, the hardware structure of the computing unit (43) is switched in accordance with a computing which is a target of execution. A controller (46) stores the internal state of the computing unit (42) in a memory (44) when a computing to the second computing. And the controller (46) controls execution of the first computing to be continued by returning the internal state stored in the memory (44) to the computing unit (42), when a computing to be executed by the computing unit (42) returns from the second computing to the first computing.

4. 发明申请

WO2003058429A2 LOGIC COMPUTING SYSTEM AND METHOD 审中-公开
标题翻译：逻辑计算系统和方法
公开(公告)号：WO2003058429A2
公开(公告)日：2003-07-17
申请号：PCT/JP2002/013442
申请日：2002-12-24
申请人： TOKYO ELECTRON DEVICE LIMITED , MITA, Takashi , NISHIHARA, Akinori
发明人： MITA, Takashi , NISHIHARA, Akinori
IPC分类号： G06F9/00
CPC分类号： G06F15/7867
摘要： A FPGA data module to be referred to as a LUT by a logic block (43) is divided into a plurality of modules. Each of a plurality of data registers (41a to 41d) stores one of the plurality of FPGA data modules. By referring to the FPGA data module(s) stores in one or more of the plurality of data registers (41a to 41d), a gate circuit (43a) and flip flop (43b) of the logic block (43) generates a logical function value of logic input data. The logical function value of the logic input data is provided as logic output data.
摘要翻译：通过逻辑块（43）被称为LUT的FPGA数据模块被分成多个模块。多个数据寄存器（41a〜41d）中的每一个存储多个FPGA数据模块之一。通过参考FPGA数据模块存储在多个数据寄存器（41a至41d）中的一个或多个中，逻辑块（43）的门电路（43a）和触发器（43b）产生逻辑功能逻辑输入数据的值。逻辑输入数据的逻辑功能值被提供为逻辑输出数据。

5. 发明申请

WO2004036450A1 METHOD OF COMPUTING FIR FILTER COEFFICIENT AND PROGRAM FOR COMPUTING SAME 审中-公开
标题翻译：计算FIR滤波器系数的方法和计算机程序
公开(公告)号：WO2004036450A1
公开(公告)日：2004-04-29
申请号：PCT/JP2003/013132
申请日：2003-10-14
申请人： THE CIRCLE FOR THE PROMOTION OF SCIENCE AND ENGINEERING , NISHIHARA, Akinori , SAMADI, Saed
发明人： NISHIHARA, Akinori , SAMADI, Saed
IPC分类号： G06F17/10
CPC分类号： H03H17/06 , H03H2017/0072
摘要： The computer executes a first operation by a first recurrence formula, receiving a filter order (positive integer) of a universal maximally flat FIR filter, the number of zeros at z=-1 (integer equal to or more than zero), and a parameter for a group delay at z=1 (rational number). The first recurrence formula includes parameters for the filter order, the number of zeros, and the group delay, and provides coefficients in Bernstein form representation of a transfer function of a universal maximally flat FIR filter. The computer then executes a second operation composed of additions, subtractions, and division by 2 by a second recurrence formula by using a resultant of the first operation as an initial value to extract impulse response coefficients of the universal maximally flat FIR filter from a resultant of the second operation.
摘要翻译：计算机通过第一递归公式执行第一操作，接收通用最大平坦FIR滤波器的滤波器顺序（正整数），z = -1（整数等于或大于零）的零数，以及参数对于在z = 1（有理数）的群延迟。第一次递归公式包括滤波器阶数，零数和组延迟的参数，并提供伯恩斯坦形式表示通用最大平坦FIR滤波器的传递函数的系数。然后，计算机通过使用第一操作的结果作为初始值，执行由加法，减法和除以2除以第二递归公式的第二操作，以从通用最大平坦FIR滤波器的结果中提取脉冲响应系数第二个操作。

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