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1. 发明申请

WO2010104990A3 PIN ELECTRONICS LIQUID COOLED MULTI-MODULE FOR HIGH PERFORMANCE, LOW COST AUTOMATED TEST EQUIPMENT 审中-公开
标题翻译： PIN电子液体冷却多模块，用于高性能，低成本自动测试设备
公开(公告)号：WO2010104990A3
公开(公告)日：2011-01-13
申请号：PCT/US2010026881
申请日：2010-03-10
申请人： TERADYNE INC , BREINLINGER KEITH , OSTERTAG EDWARD , SARTSCHEV RONALD A , TENEKETGES NICHOLAS J
发明人： BREINLINGER KEITH , OSTERTAG EDWARD , SARTSCHEV RONALD A , TENEKETGES NICHOLAS J
IPC分类号： H01L21/60 , G01R1/00
CPC分类号： G01R31/2889 , G01R31/2891
摘要： In one embodiment, a channel board-to-DIB junction multi-module is provided which includes performance critical channel electronics modules within an enclosure encasing the plurality of performance critical channel electronics modules. A coolant distribution apparatus is provided within the enclosure to provide cooling within the enclosure. A channel board connection apparatus is located at a channel board end of the channel board-to-DIB junction multi- module and a cable-less connection apparatus is located at a DIB end of the channel board-to-DIB junction multi-module.
摘要翻译：在一个实施例中，提供了一种通道板到DIB结多模块，其包括封装多个性能关键通道电子模块的外壳内的性能关键通道电子模块。冷却剂分配装置设置在外壳内以在外壳内提供冷却。通道板连接装置位于通道板至DIB结多模块的通道板端，无线连接装置位于通道板至DIB结多模块的DIB端。

2. 发明申请

WO2006071635A3 USING A PARAMETRIC MEASUREMENT UNIT FOR CONVERTER TESTING 审中-公开
标题翻译：使用参数测量单元进行转换器测试
公开(公告)号：WO2006071635A3
公开(公告)日：2006-11-02
申请号：PCT/US2005046132
申请日：2005-12-16
申请人： TERADYNE INC , WALKER ERNEST P , SARTSCHEV RONALD A
发明人： WALKER ERNEST P , SARTSCHEV RONALD A
IPC分类号： H03M1/10 , H03M1/06
CPC分类号： H03M1/1071
摘要： In one aspect, the invention is an integrated circuit (IC) for use in testing an analog-to-digital (ADC) converter includes a first channel of a parametric measurement unit (PMU) configured to send a force signal to the ADC. The IC also includes a first digital-to-analog converter (DAC) connected to the first channel of the PMU. The DAC has a DC level of accuracy of less than 1 millivolt.In another aspect, the invention is an integrated circuit (IC) for use in testing a digital-to-analog-converter-device-under-test (DACDUT). The IC includes a first channel of a parametric measurement unit (PMU) configured to send a force signal to the DACDUT and including an output port for taking measurements, a first digital-to-analog converter (DAC) connected to the first channel of the PMU and a PMU measurement path connected to the output port having a DC level of accuracy of less than 1 mV.
摘要翻译：一方面，本发明是用于测试模数（ADC）转换器的集成电路（IC），包括被配置为向ADC发送强制信号的参数测量单元（PMU）的第一通道。该IC还包括连接到PMU的第一通道的第一个数模转换器（DAC）。 DAC具有小于1毫伏的精度的DC电平。另一方面，本发明是用于测试数模转换器器件（DACDUT）的集成电路（IC）。 IC包括被配置为向DACDUT发送强制信号并包括用于进行测量的输出端口的参数测量单元（PMU）的第一通道，连接到第一通道的第一数模转换器（DAC） PMU和连接到具有小于1mV的精度的DC电平的输出端口的PMU测量路径。

3. 发明申请

WO2007038340A3 STROBE TECHNIQUE FOR TIME STAMPING A DIGITAL SIGNAL 审中-公开
标题翻译：用于时间戳数字信号的STROBE技术
公开(公告)号：WO2007038340A3
公开(公告)日：2007-11-22
申请号：PCT/US2006037100
申请日：2006-09-22
申请人： TERADYNE INC , SARTSCHEV RONALD A , WALKER ERNEST P
发明人： SARTSCHEV RONALD A , WALKER ERNEST P
IPC分类号： H04B17/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A system and apparatus generates a time-stamp to identify and record the time of an event such as an edge received in a data signal or clock signal. A set of strobe pulses can be generated by routing an external clock signal to delay elements with incrementally increasing delay values. A data signal or device under test clock signal can be applied to the input to each of a set of latches which are clocked by the strobe pulses. The set of latches can thereby capture a series of samples of the data signal or clock signal. The series of samples can be encoded as an edge time within a clock cycle. A clock cycle counter can be added to the edge time to generate the time stamp.
摘要翻译：系统和装置产生时间戳以识别和记录诸如在数据信号或时钟信号中接收的边缘的事件的时间。可以通过将外部时钟信号路由到具有递增增加的延迟值的延迟元件来产生一组选通脉冲。可以将数据信号或被测器件的器件施加到由选通脉冲定时的一组锁存器中的每一个的输入。锁存器组可由此捕获数据信号或时钟信号的一系列采样。一系列样本可以在时钟周期内编码为边沿时间。时钟周期计数器可以添加到边沿时间以生成时间戳。

4. 发明申请

WO2006071668A3 PIN ELECTRONICS WITH HIGH VOLTAGE FUNCTIONALITY 审中-公开
标题翻译：具有高电压功能的PIN电子
公开(公告)号：WO2006071668A3
公开(公告)日：2007-01-04
申请号：PCT/US2005046332
申请日：2005-12-16
申请人： TERADYNE INC , WALKER ERNEST P , SARTSCHEV RONALD A
发明人： WALKER ERNEST P , SARTSCHEV RONALD A
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： G01R31/2844
摘要： In one aspect, the invention is an integrated circuit (IC) for use in testing a device. The IC includes a pin electronics (PE) driver having an output and a pin. The IC also includes a buffer connected to the output of the PE driver and the pin. The first voltage measured at the pin is greater than a second voltage measured at the output. The IC may include a first amplifier having an input connected to a voltage source. The IC may also include a second amplifier having an input connected to the output of the PE driver.
摘要翻译：一方面，本发明是用于测试设备的集成电路（IC）。 IC包括具有输出和引脚的引脚电子（PE）驱动器。该IC还包括连接到PE驱动器和引脚的输出的缓冲器。在引脚处测量的第一个电压大于在输出端测量的第二个电压。 IC可以包括具有连接到电压源的输入的第一放大器。 IC还可以包括具有连接到PE驱动器的输出的输入的第二放大器。

5. 发明申请

WO2007038233A3 STROBE TECHNIQUE FOR TEST OF DIGITAL SIGNAL TIMING 审中-公开
标题翻译：用于数字信号时序测试的STROBE技术
公开(公告)号：WO2007038233A3
公开(公告)日：2008-10-30
申请号：PCT/US2006036912
申请日：2006-09-22
申请人： TERADYNE INC , SARTSCHEV RONALD A , WALKER ERNEST P
发明人： SARTSCHEV RONALD A , WALKER ERNEST P
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.
摘要翻译：测试系统定时方法模拟被测设备上同步时钟的时序。可以通过将边沿发生器路由到具有逐渐增加的延迟值的延迟元件来产生选通脉冲。可以将数据信号或同步时钟信号施加到由选通脉冲计时的一组锁存器中的每一个的输入。编码器可以将由此锁存的一系列样本转换成表示采样信号的边沿时间和极性的字。如果采样信号是数据信号，则该字可以存储在存储器中。如果采样信号是时钟信号，则该字路由到时钟总线，用于寻址存储器。提供时钟边沿时间和数据边沿时间之间的差异，并将其与预期值进行比较。

6. 发明申请

WO2007038339A3 STROBE TECHNIQUE FOR RECOVERING A CLOCK IN A DIGITAL SIGNAL 审中-公开
标题翻译：用于在数字信号中恢复时钟的STROBE技术
公开(公告)号：WO2007038339A3
公开(公告)日：2007-12-06
申请号：PCT/US2006037099
申请日：2006-09-22
申请人： TERADYNE INC , SARTSCHEV RONALD A , WALKER ERNEST P
发明人： SARTSCHEV RONALD A , WALKER ERNEST P
IPC分类号： H04L7/00
CPC分类号： G01R31/31937 , G01R31/31726 , G11C29/56 , G11C29/56004 , G11C29/56012
摘要： A method and apparatus is provided to recover clock information embedded in a digital signal such as a digital signal A set of strobe pulses can be generated by routing an edge generator to a delay elements with incrementally increasing delay values A set of latches triggered by incrementally delayed signals from the edge generator can capture samples of the data signal An encoder (84) can convert the samples to a word representing edge time and polarity of the sampled signal The word representing edge time can be stored in memory (86) An accumulator can collect the average edge time over N samples (88) The average edge time can be adjusted with a fixed de-skew value to form the extracted clock information The extracted clock information can be used as pointer to the words stored in memory
摘要翻译：提供了一种方法和装置来恢复嵌入在诸如数字信号的数字信号中的时钟信号。可以通过将边沿发生器路由到具有递增增加的延迟值的延迟元件来产生一组选通脉冲。通过增量延迟触发一组锁存器来自边缘发生器的信号可以捕获数据信号的采样编码器（84）可以将样本转换为表示采样信号的边沿时间和极性的字。表示边沿时间的字可以存储在存储器中（86）累加器可以收集平均边缘时间超过N个样本（88）平均边沿时间可以用固定的去偏移值调整以形成提取的时钟信息提取的时钟信息可以用作指向存储在存储器中的字的指针

7. 发明申请

WO2006068937A3 A METHOD AND SYSTEM FOR PRODUCING SIGNALS TO TEST SEMICONDUCTOR DEVICES 审中-公开
标题翻译：用于生成到测试半导体器件的信号的方法和系统
公开(公告)号：WO2006068937A3
公开(公告)日：2007-01-11
申请号：PCT/US2005045606
申请日：2005-12-16
申请人： TERADYNE INC , WALKER ERNEST P , SARTSCHEV RONALD A
发明人： WALKER ERNEST P , SARTSCHEV RONALD A
IPC分类号： G01R31/26
CPC分类号： G01R31/31924
摘要： A method of and system for producing signals to test semiconductor devices includes a pin electronic (PE) stage for providing a parametric measurement unit (PMU) current test signal to a semiconductor device under test. The PE stage also senses a response from the semiconductor device under test.
摘要翻译：用于产生信号以测试半导体器件的方法和系统包括用于向被测半导体器件提供参数测量单元（PMU）电流测试信号的引脚电子（PE）级。 PE阶段还可以检测来自被测半导体器件的响应。

8. 发明申请

WO2006068936A3 A METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICES 审中-公开
标题翻译：一种用于测试半导体器件的方法和系统
公开(公告)号：WO2006068936A3
公开(公告)日：2006-09-08
申请号：PCT/US2005045605
申请日：2005-12-16
申请人： TERADYNE INC , WALKER ERNEST P , SARTSCHEV RONALD A
发明人： WALKER ERNEST P , SARTSCHEV RONALD A
IPC分类号： G01R31/26
CPC分类号： G01R31/31924
摘要： A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device.
摘要翻译：半导体器件测试器包括用于产生DC测试信号的参数测量单元（PMU）级和用于产生用于测试半导体器件的AC测试信号的引脚电子（PE）级。驱动器电路能够向半导体器件提供DC测试信号的一个版本和AC测试信号的版本。

9. 发明申请

WO2006066112A3 USING PARAMETRIC MEASUREMENT UNITS AS A SOURCE OF POWER FOR A DEVICE UNDER TEST 审中-公开
标题翻译：使用参数测量单元作为测试设备的功率源
公开(公告)号：WO2006066112A3
公开(公告)日：2006-08-17
申请号：PCT/US2005045718
申请日：2005-12-16
申请人： TERADYNE INC , WALKER ERNEST P , SARTSCHEV RONALD A
发明人： WALKER ERNEST P , SARTSCHEV RONALD A
IPC分类号： G01R31/02 , G01R31/26 , G01R31/28
CPC分类号： G01R31/2886 , G01R31/2839 , G01R31/2889 , G01R31/3004
摘要： An apparatus for providing current to a device under test includes a first parametric measurement unit configured to provide current to the device, and a second parametric measurement unit configured to provide current to the device. The current from the second parametric measurement unit augments the current from the first parametric measurement unit at the device.
摘要翻译：用于向被测设备提供电流的装置包括被配置为向所述设备提供电流的第一参数测量单元和被配置为向所述设备提供电流的第二参数测量单元。来自第二参数测量单元的电流从装置上的第一参数测量单元增加电流。

10. 发明申请

WO0208776A3 AUTOMATIC TEST EQUIPMENT WITH NARROW OUTPUT PULSES 审中-公开
标题翻译：带有窄输出脉冲的自动测试设备
公开(公告)号：WO0208776A3
公开(公告)日：2002-06-06
申请号：PCT/US0122472
申请日：2001-07-17
申请人： TERADYNE INC
发明人： SARTSCHEV RONALD A
IPC分类号： G01R31/319
CPC分类号： G01R31/31928 , G01R31/31922
摘要： Automatic test equipment suitable for testing high speed semiconductor devices. The test equipment includes a formatter circuit with a flip flop that produces an output in the desired format even if the edge signals that control the setting and resetting of the flip flop overlap. The flip flop allows the test system to generate outputs with narrow pulses, and can generate output pulses that are narrower than the controlling edge signals.
摘要翻译：自动测试设备适用于测试高速半导体器件。测试设备包括一个带有触发器的格式化器电路，即使控制触发器的设置和复位的边沿信号重叠，该触发器也可以产生所需格式的输出。触发器允许测试系统以窄脉冲产生输出，并且可以产生比控制边沿信号更窄的输出脉冲。

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