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1. 发明申请

WO2014163099A2 RECONFIGURABLE LOGIC DEVICE 审中-公开
标题翻译：可重构逻辑器件
公开(公告)号：WO2014163099A2
公开(公告)日：2014-10-09
申请号：PCT/JP2014059703
申请日：2014-04-02
申请人： TAIYO YUDEN KK
发明人： SATO MASAYUKI , SATO KOUSHI , KATSU MITSUNORI , SHIMIZU ISAO
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , G06F17/5054 , H03K19/17744 , H03K19/1776
摘要： [Problem] To enable the provision of a reconfigurable logic device that has a small surface area and is highly reconfigurable. [Solution] A reconfigurable logic device having a plurality of multi lookup table units and in which a plurality of logic circuits can be configured according to configuration data information. Each multi lookup table has: configuration memory that stores configuration data; a data input line; a data output line; a reconfigurable logic multiplexer that, in response to the configuration data, selectively links data input from the data input line and data output to the data output line and/or that, in response to the configuration data, outputs, to the data output line, data logically computed pertaining to the data input. Adjacent multi lookup tables are connected by the data input lines and data output lines.
摘要翻译： [问题]能够提供具有小表面积且高度可重构的可重构逻辑器件。 [解决方案]具有多个多查找表单元的可重构逻辑设备，其中可以根据配置数据信息来配置多个逻辑电路。每个多查询表有：配置存储器，用于存储配置数据; 数据输入线数据输出线; 可重配置逻辑多路复用器，响应于配置数据，选择性地将从数据输入线输入的数据输出和输出到数据输出线的数据输出，和/或响应于配置数据将数据输出到数据输出线，与数据输入逻辑计算的数据。相邻的多查找表通过数据输入线和数据输出线连接。

2. 发明申请

WO2014080872A3 LOGIC CONFIGURATION METHOD FOR RECONFIGURABLE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：用于可重构半导体器件的逻辑配置方法
公开(公告)号：WO2014080872A3
公开(公告)日：2014-07-17
申请号：PCT/JP2013081087
申请日：2013-11-19
申请人： TAIYO YUDEN KK
发明人： SATO MASAYUKI , SHIMIZU ISAO
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , G06F17/505 , G06F17/5077 , H03K19/173 , H03K19/17728 , H03K19/17736 , H03K19/17748
摘要： Provided is a logic configuration method for a semiconductor device having a plurality of storage units provided with a plurality of memory cells, wherein: each storage unit is configured to store truth table data in the memory cells thereof, the truth table data being for outputting a logic value for an address input, and to operate as a logic circuit; the storage units have n (where n is 2 or a higher integer) times two pairs of an input and output line; the n times two output lines from one storage unit among the storage units are connected to the n input lines of another two storage units; and the logic configuration method generates, on the basis of the circuit description described in the circuit configuration, a net list having circuit connection information, extracts a logic cone from the net list, and generates truth data for the plurality of storage units, which constitute the logic cone, in the storage unit stage number corresponding to the number obtained by dividing the number of input lines to the logic cone by n/2.
摘要翻译：提供一种半导体器件的逻辑配置方法，所述半导体器件具有设置有多个存储器单元的多个存储单元，其中：每个存储单元被配置为将真值表数据存储在其存储器单元中，所述真值表数据用于输出地址输入的逻辑值，并作为逻辑电路工作; 存储单元具有n（其中n是2或更大的整数）乘以两对输入和输出线; 来自存储单元中的一个存储单元的n次两条输出线连接到另外两个存储单元的n条输入线; 并且逻辑配置方法基于电路配置中描述的电路描述产生具有电路连接信息的网表，从网表中提取逻辑锥并且为多个存储单元生成真值数据，所述真值数据构成逻辑锥在存储单元级数中对应于通过将输入线的数量除以逻辑锥得到的数量n / 2。

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