专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2008150555A1 METHOD FOR COMPENSATION OF PROCESS-INDUCED PERFORMANCE VARIATION IN A MOSFET INTEGRATED CIRCUIT 审中-公开
标题翻译： MOSFET集成电路中过程诱导性能变化补偿的方法
公开(公告)号：WO2008150555A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/051355
申请日：2008-01-17
申请人： SYNOPSYS, INC. , MOROZ, Victor , PRAMANIK, Dipankar , SINGHAL, Kishore , LIN, Xi-Wei
发明人： MOROZ, Victor , PRAMANIK, Dipankar , SINGHAL, Kishore , LIN, Xi-Wei
IPC分类号： G01R31/26
CPC分类号： G06F17/5068 , G06F17/5036
摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
摘要翻译：用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。该方法的第一步是从阵列中选择一个用于分析的晶体管。该方法根据需要在阵列的晶体管之间循环。接下来分析所选晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定布局邻域引起的驱动电流变化。该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

2. 发明申请

WO2010087884A1 BOOSTING TRANSISTOR PERFORMANCE WITH NON-RECTANGULAR CHANNELS 审中-公开
标题翻译：提高非矩形通道的晶体管性能
公开(公告)号：WO2010087884A1
公开(公告)日：2010-08-05
申请号：PCT/US2009/062635
申请日：2009-10-29
申请人： SYNOPSYS, INC. , MOROZ, Victor , CHOI, Munkang , LIN, Xi-Wei
发明人： MOROZ, Victor , CHOI, Munkang , LIN, Xi-Wei
IPC分类号： H01L27/02 , H01L29/10 , H01L21/266 , G06F17/50
CPC分类号： G06F17/5072 , H01L21/266 , H01L27/0207 , H01L29/1033 , H01L29/41758
摘要： Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.
摘要翻译：粗略地描述，本发明包括用于集成电路的布局和掩模，其中晶体管的扩散形状包括在一个或两个横向相对侧上的横向延伸的点动，该点动具有内角和外角，其中至少一个位于相对于栅极导体纵向，使得在将扩散形状平版印刷到集成电路上时，角部将圆形并且至少部分地延伸到沟道区域中。本发明还包括用于引入这种点动的系统和方法以及用于具有非矩形通道区域的集成电路器件的方面，其中沟道区域在与栅极区域相比较宽的位置处比栅极下方的其它纵向位置更宽。

3. 发明申请

WO2014005078A1 SRAM LAYOUTS 审中-公开
公开(公告)号：WO2014005078A1
公开(公告)日：2014-01-03
申请号：PCT/US2013/048692
申请日：2013-06-28
申请人： SYNOPSYS, INC. , LIN, Xi-Wei , MOROZ, Victor
发明人： LIN, Xi-Wei , MOROZ, Victor
IPC分类号： G11C11/41
CPC分类号： G06F17/5072 , G06F17/5068 , G11C11/412 , G11C11/419 , H01L21/823828 , H01L27/0207 , H01L27/1104
摘要： Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods.
摘要翻译：大体上描述的是，SRAM阵列中的单元布局被重新布置，使得期望具有灵活性的用于晶体管的栅电极是沿着与用于使用不同通道的灵活性的晶体管不同的磁道形成的需要长度。这样的重新布置不仅允许设备比例的优化，而且在某些实施方式中也可以减小而不是增加单元面积。描述具体示例布局。本发明还涉及布局文件，宏小区，光刻掩模和结合这些原理的集成电路装置以及制造方法。

4. 发明申请

WO2022015930A1 FABRICATION TECHNIQUE FOR FORMING ULTRA-HIGH DENSITY INTEGRATED CIRCUIT COMPONENTS 审中-公开
公开(公告)号：WO2022015930A1
公开(公告)日：2022-01-20
申请号：PCT/US2021/041749
申请日：2021-07-15
申请人： SYNOPSYS, INC.
发明人： LIN, Xi-Wei , MOROZ, Victor
IPC分类号： H01L21/033 , H01L27/02 , H01L27/11
摘要： A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

5. 发明申请

WO2023038647A1 POWER ROUTING FOR 2.5D OR 3D INTEGRATED CIRCUITS 审中-公开
公开(公告)号：WO2023038647A1
公开(公告)日：2023-03-16
申请号：PCT/US2021/050986
申请日：2021-09-17
申请人： SYNOPSYS, INC.
发明人： LIN, Xi-Wei , MOROZ, Victor
IPC分类号： H01L23/528 , H01L21/768 , H01L21/74 , H01L23/498 , H01L23/535 , H01L25/065
摘要： Embodiments relate to an electronic circuit implemented using a first integrated circuit die, a second integrated circuit die, and an interposer connecting the first integrated circuit die to the second integrated circuit die. The first integrated circuit die implements a first electronic circuit. The first integrated circuit die includes a first set of contacts on a bottom surface, a buried power rail (BPR), and a plurality of through-silicon vias (TSV) for connecting the BPR to the first set of contacts. The interposer includes a second set of contacts and a power delivery network (PDN). Each contact of the second set of contact corresponds to a contact of the first set of contacts of the first integrated circuit die. The PDN is configured to route a power supply voltage to the second set of contacts.

6. 发明申请

WO2022119570A1 FIN PATTERNING TO REDUCE FIN COLLAPSE AND TRANSISTOR LEAKAGE 审中-公开
公开(公告)号：WO2022119570A1
公开(公告)日：2022-06-09
申请号：PCT/US2020/063071
申请日：2020-12-03
申请人： SYNOPSYS, INC.
发明人： MOROZ, Victor , LIN, Xi-Wei
IPC分类号： H01L29/66 , H01L29/78 , H01L21/306
摘要： At least one fin structure may be created on a silicon substrate. Next, a width of the at least one fin structure may be decreased by applying one or more iterations of a self-limiting fin etch process.

7. 发明申请

WO2022015926A1 FORMING A WRAP-AROUND CONTACT TO CONNECT A SOURCE OR DRAIN EPITAXIAL GROWTH OF A COMPLIMENTARY FIELD EFFECT TRANSISTOR (CFET) TO A BURIED POWER RAIL (BPR) OF THE CFET 审中-公开
公开(公告)号：WO2022015926A1
公开(公告)日：2022-01-20
申请号：PCT/US2021/041743
申请日：2021-07-15
申请人： SYNOPSYS, INC.
发明人： LIN, Xi-Wei , MOROZ, Victor
IPC分类号： H01L21/822 , H01L21/8238
摘要： A method of forming an electrical connection between a buried power rail (BPR) of an unfinished complementary field effect transistor (CFET) and a source or drain epitaxial growth of a lower level of the CFET is provided. The method includes performing silicon epitaxial growth (302) in a lower level of the CFET, adding a contact material (332) to a portion of an exposed portion of the silicon epitaxial growth in the lower level, the exposed portion of the silicon epitaxial growth being located in a vertical slot (309) of the unfinished CFET structure, adding a conductive material (334) within a vertical channel (322), the conductive material being in contact with the added contact material and the BPR (304) to form an electrical connection between the portion of the exposed portion of the silicon epitaxial growth and the BPR and etching back a portion of the added conductive material within the vertical channel.

8. 发明申请

WO2022015924A1 EPITAXIAL GROWTH OF SOURCE AND DRAIN MATERIALS IN A COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) 审中-公开
公开(公告)号：WO2022015924A1
公开(公告)日：2022-01-20
申请号：PCT/US2021/041740
申请日：2021-07-15
申请人： SYNOPSYS, INC.
发明人： LIN, Xi-Wei , MOROZ, Victor
IPC分类号： H01L21/822 , H01L21/8238 , H01L29/775
摘要： A method of performing epitaxial growth of a source and drain on levels of a complementary field effect transistor (CFET) is provided. The method includes depositing a first blocking material (302) in a vertical channel of an unfinished CFET structure, oxidizing silicon at a surface of an upper level of the CFET to provide one or more S1O2 protective layers (312), etching away a portion of silicon from a lower level of the CFET to form a lateral recess that is exposed to the vertical channel, and performing silicon epitaxial growth in the lower level of the unfinished CFET structure. Further, after the silicon epitaxial growth on the lower level, the method includes depositing a second blocking material (342) in the vertical channel to cover at least a portion of the silicon epitaxial growth in the lower level, removing the Si02 protective layer, and performing epitaxial growth on the upper level.

9. 发明申请

WO2017024075A1 PRE-SILICON DESIGN RULE EVALUATION 审中-公开
标题翻译： PRE-SILICON设计规则评估
公开(公告)号：WO2017024075A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/045425
申请日：2016-08-03
申请人： SYNOPSYS, INC.
发明人： MOROZ, Victor , EL SAYED, Karim , MA, Terry Sylvan Kam-Chiu , LIN, Xi-Wei , LU, Qiang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036
摘要： Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.
摘要翻译：粗略地描述，用于开发用于开发中的制造工艺的一组设计规则的方法包括针对制造工艺的几个候选DRUT中的每一个，基于DRUT铺设我们的逻辑单元，所述逻辑单元具有至少一个晶体管和至少一个互连，根据制造过程和布局模拟逻辑单元的制造，模拟逻辑单元结构的行为，包括表征第一晶体管和第一互连的组合行为，评估逻辑单元结构的性能根据表征的行为，并且与数据库中的DRUT的指示相关联地记录指示逻辑单元的性能的值。数据库可用于为制造过程选择最佳DRUT。

10. 发明申请

WO2023004052A1 INPUT/OUTPUT DEVICES THAT ARE COMPATIBLE WITH GATE-ALL-AROUND TECHNOLOGY 审中-公开
公开(公告)号：WO2023004052A1
公开(公告)日：2023-01-26
申请号：PCT/US2022/037891
申请日：2022-07-21
申请人： SYNOPSYS, INC.
发明人： MOROZ, Victor , LEFFERTS, Robert B. , LIN, Xi-Wei , CHOI, Munkang
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
摘要： An integrated circuit (IC) chip may include a first gate-all-around (GAA) device (102) and a second GAA device (202). The first GAA device may include a first set of silicon dioxide structures (108) around a first set of silicon channels (106), a first set of hafnium dioxide structures (110) around the first set of silicon dioxide structures, and a first metal structure (112) around the first set of hafnium dioxide structures. The second GAA device may include a second set of silicon dioxide structures (206) around a second set of silicon channels (204), and a second metal structure (208) around the second set of silicon dioxide structures. Each silicon dioxide structure in the first set of silicon dioxide structures may have a first thickness. Each silicon dioxide structure in the second set of silicon dioxide structures may have a second thickness, which is greater than the first thickness.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式