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1. 发明申请

WO2009058449A1 METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：用于抑制半导体衬底中的晶体缺陷的方法
公开(公告)号：WO2009058449A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/071572
申请日：2008-07-30
申请人： SYNOPSYS, INC. , MOROZ, Victor , PRAMANIK, Dipankar
发明人： MOROZ, Victor , PRAMANIK, Dipankar
IPC分类号： H01L21/322
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L29/1054 , H01L29/1079 , H01L29/7848
摘要： A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
摘要翻译：一种用于抑制在晶格中的掺杂剂注入之后的晶格中的渗漏促进缺陷的形成的方法。该方法提供原子的压缩层，这些原子的尺寸大于晶格构件原子的尺寸。然后将晶格退火足以使间隙缺陷原子从压缩层发射的时间，并且以这种方式，在离压缩层一定距离处的晶格中形成能量稳定的缺陷。

2. 发明申请

WO2013032809A1 ATOMIC LAYER DEPOSITION OF METAL OXIDE MATERIALS FOR MEMORY APPLICATIONS 审中-公开
标题翻译：用于存储器应用的金属氧化物材料的原子层沉积
公开(公告)号：WO2013032809A1
公开(公告)日：2013-03-07
申请号：PCT/US2012/051865
申请日：2012-08-22
申请人： INTERMOLECULAR, INC. , WANG, Yun , GOPAL, Vidyut , HASHIM, Imran , PRAMANIK, Dipankar , CHIANG, Tony
发明人： WANG, Yun , GOPAL, Vidyut , HASHIM, Imran , PRAMANIK, Dipankar , CHIANG, Tony
IPC分类号： H01L21/20 , B82Y40/00
CPC分类号： H01L45/145 , C23C16/40 , C23C16/45525 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/2463 , H01L45/08 , H01L45/1266 , H01L45/146 , H01L45/1608 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices, such as a ReRAM cells, and methods for manufacturing such memory devices, which includes optimized, atomic layer deposition (ALD) processes for forming metal oxide film stacks. The metal oxide film stacks contain a metal oxide coupling layer disposed on a metal oxide host layer, each layer having different grain structures/sizes. The interface disposed between the metal oxide layers facilitates oxygen vacancy movement. In many examples, the interface is a misaligned grain interface containing numerous grain boundaries extending parallel to the electrode interfaces, in contrast to the grains in the bulk film extending perpendicular to the electrode interfaces. As a result, oxygen vacancies are trapped and released during switching without significant loss of vacancies. Therefore, the metal oxide film stacks have improved switching performance and reliability during memory cell applications compared to traditional hafnium oxide based stacks of previous memory cells.
摘要翻译：本发明的实施例一般涉及非易失性存储器件，例如ReRAM单元，以及用于制造这种存储器件的方法，其包括用于形成金属氧化物膜堆叠的优化的原子层沉积（ALD）工艺。金属氧化物膜堆叠包含设置在金属氧化物主体层上的金属氧化物耦合层，每个层具有不同的晶粒结构/尺寸。设置在金属氧化物层之间的界面有助于氧空位移动。在许多示例中，与垂直于电极界面延伸的体膜中的晶粒相反，界面是不对准的晶界，其包含平行于电极界面延伸的许多晶界。因此，氧空缺在切换期间被捕获和释放，而空位明显损失。因此，与以前的存储单元的传统的基于氧化铪的堆叠相比，金属氧化物膜堆叠在存储单元应用中具有改进的开关性能和可靠性。

3. 发明申请

WO2008150554A3 METHOD FOR RAPID ESTIMATION OF LAYOUT-DEPENDENT THRESHOLD VOLTAGE VARIATION IN A MOSFET ARRAY 审中-公开
标题翻译： MOSFET阵列快速估计依赖于阈值电压变化的方法
公开(公告)号：WO2008150554A3
公开(公告)日：2009-12-23
申请号：PCT/US2008051343
申请日：2008-01-17
申请人： SYNOPSYS INC , MOROZ VICTOR , PRAMANIK DIPANKAR
发明人： MOROZ VICTOR , PRAMANIK DIPANKAR
IPC分类号： G06F17/50
CPC分类号： H01L21/823412 , G06F17/5036 , H01L21/823425 , H01L27/0207
摘要： An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si / STI edges on the selected area as well as channel areas and their associated gate / Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.
摘要翻译：用于估计集成电路布局中阈值电压的布局引起的变化的自动化方法。该方法开始于在布局内选择扩散区域以进行分析的步骤。然后，系统识别所选区域的Si / STI边缘以及通道区域及其相关的栅极/ Si边缘。接下来，识别每个识别的通道区域中的阈值电压变化，这需要由于纵向方向的影响而计算阈值电压变化的进一步步骤; 计算由于横向影响引起的阈值电压变化; 并且将纵向和横向变化组合以提供整体变化。最后，通过组合来自各个通道变化的变化来确定总体变化。

4. 发明申请

WO2009109996A3 NOVEL CATIONIC AMPHIPHILES WITH QUINIC ACID HEAD-GROUPS FOR DNA VACCINATION 审中-公开
公开(公告)号：WO2009109996A3
公开(公告)日：2009-09-11
申请号：PCT/IN2009/000119
申请日：2009-02-24
申请人： COUNCIL OF SCIENTIFIC & INDUSTRIAL RESEARCH , KARMALI, Priya, Prakash , PRAMANIK, Dipankar , MAJETI, Bharat, Kumar , CHAUDHURI, Arabinda , SISTLA, Ramakrishna
发明人： KARMALI, Priya, Prakash , PRAMANIK, Dipankar , MAJETI, Bharat, Kumar , CHAUDHURI, Arabinda , SISTLA, Ramakrishna
IPC分类号： C07C235/40 , A61K31/16 , A61K48/00
摘要： The present invention provides a novel series of glycomimicking cationic amphiphiles containing quinic acid head-groups and methods for preparing the said cationic amphiphiles. The invention provides novel compositions containing the said amphiphiles with remarkable gene transfer properties. Furthermore, the present invention provides methods for producing immune response in mice using the above-mentioned formulations containing the said cationic amphiphiles and genetic materials encoding immunogenic antigens. The area of medical science that is likely to benefit most from the present invention is genetic immunization.

5. 发明申请

WO2013043561A1 ATOMIC LAYER DEPOSITION OF HAFNIUM AND ZIRCONIUM OXIDES FOR MEMORY APPLICATIONS 审中-公开
标题翻译：用于存储器应用的铪和氧化锆的原子层沉积
公开(公告)号：WO2013043561A1
公开(公告)日：2013-03-28
申请号：PCT/US2012/055851
申请日：2012-09-18
申请人： INTERMOLECULAR, INC. , WANG, Yun , GOPAL, Vidyut , HASHIM, Imran , PRAMANIK, Dipankar , CHIANG, Tony
发明人： WANG, Yun , GOPAL, Vidyut , HASHIM, Imran , PRAMANIK, Dipankar , CHIANG, Tony
IPC分类号： H01L21/20
CPC分类号： H01L45/146 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1616
摘要： Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal- rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.
摘要翻译：本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。在一个实例中，金属氧化物本体层含有富含金属的氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。

6. 发明申请

WO2013025968A1 LOW TEMPERATURE MIGRATION ENHANCED SI-GE EPITAXY WITH PLASMA ASSISTED SURFACE ACTIVATION 审中-公开
标题翻译：低温移动增强SI-GE外形等离子体辅助表面激活
公开(公告)号：WO2013025968A1
公开(公告)日：2013-02-21
申请号：PCT/US2012/051278
申请日：2012-08-17
申请人： INTERMOLECULAR, INC. , KRAUS, Philip, A. , PRAMANIK, Dipankar , BORISOV, Boris
发明人： KRAUS, Philip, A. , PRAMANIK, Dipankar , BORISOV, Boris
IPC分类号： H01L21/302
CPC分类号： C23C16/45551 , C23C16/42 , C23C16/4554 , C23C16/483 , C30B25/12 , C30B29/06 , C30B29/08 , H01L21/02532 , H01L21/0262
摘要： Epitaxial films are grown by alternately exposed to precursor dosing regions, inert gas plasma regions, hydrogen-containing plasma regions, chlorine- containing plasma and metrology regions, or regions where an atomic hydrogen source is located. Alternately, laser irradiation techniques may be substituted for the plasma energy in some of the processing regions. The film growth process can be implemented at substrate temperatures between about 25C and about 600C, together with optional exposures to laser irradiation to cause the surface of the film to melt or to experience a near-melt condition.
摘要翻译：外延膜通过交替地暴露于前体给料区域，惰性气体等离子体区域，含氢等离子体区域，含氯等离子体和计量区域或原子氢源所在的区域而生长。或者，激光照射技术可以替代一些处理区域中的等离子体能量。膜生长过程可以在约25℃至约600℃之间的衬底温度下进行，以及可选地暴露于激光照射以使膜的表面熔化或经历近熔融状态。

7. 发明申请

WO2013016027A1 MEMORY DEVICE WITH A TEXTURED LOWERED ELECTRODE 审中-公开
标题翻译：具有纹理下降的电极的存储器件
公开(公告)号：WO2013016027A1
公开(公告)日：2013-01-31
申请号：PCT/US2012/046634
申请日：2012-07-13
申请人： INTERMOLECULAR, INC. , PRAMANIK, Dipankar
发明人： PRAMANIK, Dipankar
IPC分类号： H01L29/02
CPC分类号： H01L45/1253 , H01L21/0332 , H01L21/32139 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1641
摘要： Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack.
摘要翻译：本发明的实施例一般涉及用于制造这种存储器件的存储器件和方法。在一个实施例中，提供了一种用于形成具有纹理电极的存储器件的方法，包括在设置在衬底上的下电极上形成氧化硅层，在氧化硅层上形成金属颗粒，其中金属颗粒分开设置彼此在氧化硅层上。该方法还包括在金属颗粒之间蚀刻，同时去除氧化硅层的一部分并在下电极内形成槽，通过湿法蚀刻工艺除去金属颗粒和剩余的氧化硅层，同时显露由设置在下电极，在槽内和下电极的峰上形成金属氧化物膜堆叠，并在金属氧化物膜堆叠上形成上电极。

8. 发明申请

WO2012078831A2 SMART POLYMERIC NANOPARTICLES WHICH OVERCOME MULTIDRUG RESISTANCE TO CANCER CHEMOTHERAPEUTICS AND TREATMENT-RELATED SYSTEMIC TOXICITY 审中-公开
标题翻译：智能聚合物纳米颗粒克服癌症化疗药物和治疗相关系统毒性的多重抗药性
公开(公告)号：WO2012078831A2
公开(公告)日：2012-06-14
申请号：PCT/US2011/063870
申请日：2011-12-08
申请人： THE JOHNS HOPKINS UNIVERSITY , MAITRA, Anirban , PRAMANIK, Dipankar
发明人： MAITRA, Anirban , PRAMANIK, Dipankar
IPC分类号： A61K47/48 , A61K9/127 , C08F20/56 , C08F20/06 , A61K31/7042 , A61K31/704 , A61P35/00
CPC分类号： A61K31/12 , A61K9/0019 , A61K9/5138 , A61K31/704 , A61K31/7042 , A61K45/06 , C08F220/06 , C08F220/56 , C08F226/10 , A61K2300/00
摘要： Polymeric nanoparticles with a hydrophobic core that encapsulates curcumin and a hydrophilic shell with one or more chemotherapeutic agents (e.g., doxorubicin) associated with the shell surface are formed from N-isopropylacryl amide (NEPAAM), acrylic acid (AA), and at least one vinyl monomer selected from the group consisting of vinyl acetate, 4-vinyl benzoic acid, methylmethacrylate, vinylmethacrylate, N-vinylpyrrolidone, N-vinyl piperidone, N-vinyl caprolacum, N-vinyl carbazole, and styrene, where the ΝΓΡΑΑΜ, the AA, and the vinyl monomer are present at molar ratios of 50-70:10-30: 10-30 for NIPAAM:AA:vmyl monomer. These nanoparticles effectively overcome multidrug resistance and ameliorate cardiomyopathy in vivo.
摘要翻译：具有疏水核心的聚合物纳米颗粒由N-异丙基丙烯酰胺（NEPAAM），丙烯酸形成的包封姜黄素和具有一种或多种与壳表面缔合的化学治疗剂（例如多柔比星）的亲水性壳的N-异丙基丙烯酰胺（AA）和至少一种选自乙酸乙烯酯，4-乙烯基苯甲酸，甲基丙烯酸甲酯，甲基丙烯酸乙烯酯，N-乙烯基吡咯烷酮，N-乙烯基哌啶酮，N-乙烯基己内酯，N-乙烯基咔唑和苯乙烯的乙烯基单体其中NIPAA，AA和乙烯基单体对于NIPAAM：AA：乙烯基单体以50-70:10-30:10-30的摩尔比存在。这些纳米粒子有效地克服了多种药物的耐药性并改善了体内心肌病。

9. 发明申请

WO2009058450A1 METHOD FOR TRAPPING IMPLANT DAMAGE IN A SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：用于在半导体衬底中捕获植入物损伤的方法
公开(公告)号：WO2009058450A1
公开(公告)日：2009-05-07
申请号：PCT/US2008/071579
申请日：2008-07-30
申请人： SYNOPSYS, INC. , MOROZ, Victor , PRAMANIK, Dipankar
发明人： MOROZ, Victor , PRAMANIK, Dipankar
IPC分类号： H01L21/265 , H01L29/772
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/3221 , H01L21/324
摘要： A method for minimizing the effects of defects produced in a implantated area of a crystal lattice during dopant implantation in the lattice. The method begins with the step of implanting a trap layer of trap atoms, the trap atoms having a size less than that of the lattice member atoms. After implantation, the lattice is annealed for a time sufficient for interstitial defect atoms to be emitted from the defect area. In that manner, energetically stable pairs are formed between trap atoms and emitted interstitial atoms.
摘要翻译：一种用于最小化在晶格中的掺杂剂注入期间在晶格的注入区域中产生的缺陷的影响的方法。该方法开始于注入陷阱原子的捕获层的步骤，陷阱原子的尺寸小于晶格构件原子的尺寸。植入后，晶格退火足以使间隙缺陷原子从缺陷区域发射的时间。以这种方式，在陷阱原子和发射的间隙原子之间形成能量稳定的对。

10. 发明申请

WO2008150555A1 METHOD FOR COMPENSATION OF PROCESS-INDUCED PERFORMANCE VARIATION IN A MOSFET INTEGRATED CIRCUIT 审中-公开
标题翻译： MOSFET集成电路中过程诱导性能变化补偿的方法
公开(公告)号：WO2008150555A1
公开(公告)日：2008-12-11
申请号：PCT/US2008/051355
申请日：2008-01-17
申请人： SYNOPSYS, INC. , MOROZ, Victor , PRAMANIK, Dipankar , SINGHAL, Kishore , LIN, Xi-Wei
发明人： MOROZ, Victor , PRAMANIK, Dipankar , SINGHAL, Kishore , LIN, Xi-Wei
IPC分类号： G01R31/26
CPC分类号： G06F17/5068 , G06F17/5036
摘要： An automated method for compensating for process-induced variations in threshold voltage and drive current in a MOSFET integrated circuit. The method's first step is selecting a transistor for analysis from the array. The method loops among the transistors of the array as desired. Next the design of the selected transistor is analyzed, including the steps of determining threshold voltage variations induced by layout neighborhood; determining drive current variations induced by layout neighborhood. The method then proceeds by attempting to compensate for any determined variations by varying the length of the transistor gate. The method can further include the step of identifying any shortcoming in compensation by varying contact spacing.
摘要翻译：用于补偿MOSFET集成电路中阈值电压和驱动电流的过程引起的变化的自动化方法。该方法的第一步是从阵列中选择一个用于分析的晶体管。该方法根据需要在阵列的晶体管之间循环。接下来分析所选晶体管的设计，包括确定由布局邻域引起的阈值电压变化的步骤; 确定布局邻域引起的驱动电流变化。该方法然后通过改变晶体管栅极的长度来尝试补偿任何确定的变化。该方法还可以包括通过改变接触间距来识别补偿中的任何缺点的步骤。

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