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1. 发明申请

WO2010002515A3 LOW-COST SUBSTRATES HAVING HIGH-RESISTIVITY PROPERTIES AND METHODS FOR THEIR MANUFACTURE 审中-公开
标题翻译：具有高电阻率特性的低成本基板及其制造方法
公开(公告)号：WO2010002515A3
公开(公告)日：2010-07-29
申请号：PCT/US2009044810
申请日：2009-05-21
申请人： SOITEC SILICON ON INSULATOR , MAZURE CARLOS , NGUYEN BICH-YEN
发明人： MAZURE CARLOS , NGUYEN BICH-YEN
IPC分类号： H01L21/20
CPC分类号： H01L21/76251
摘要： In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.
摘要翻译：在一个实施例中，本发明提供了这样的基板，其被构造成使得在其顶层中制造的器件具有与在标准高电阻率基板中制造的相同器件类似的性质。本发明的衬底包括具有标准电阻率的支撑体，布置在支撑衬底上的具有高电阻率，优选大于约1000欧姆 - 厘米的半导体层，布置在高电阻率层上的绝缘层，以及顶层排列在绝缘层上。本发明还提供了制造这种衬底的方法。

2. 发明申请

WO2010002516A2 LOW-COST DOUBLE STRUCTURE SUBSTRATES AND METHODS FOR THEIR MANUFACTURE 审中-公开
标题翻译：低成本双重结构基板及其制造方法
公开(公告)号：WO2010002516A2
公开(公告)日：2010-01-07
申请号：PCT/US2009044825
申请日：2009-05-21
申请人： SOITEC SILICON ON INSULATOR , NGUYEN BICH-YEN , MAZURE CARLOS
发明人： NGUYEN BICH-YEN , MAZURE CARLOS
IPC分类号： H01L21/20
CPC分类号： H01L21/76254 , H01L21/76256
摘要： In preferred embodiments, the invention provides substrates that include a support, a first insulating layer arranged on the support, a non-mono-crystalline semi-conducting layer arranged on the first insulating layer, a second insulating layer arranged on the non-mono-crystalline semi-conducting layer; and top layer disposed on the second insulating layer. Additionally, a first gate electrode can be formed on the top layer and a second gate electrode can be formed in the non-mono-crystalline semi-conducting layer. The invention also provides methods for manufacture of such substrates.
摘要翻译：在优选实施例中，本发明提供了包括支撑件，布置在支撑件上的第一绝缘层，布置在第一绝缘层上的非单晶半导体层的衬底，布置在非单晶半导体层上的第二绝缘层，结晶半导体层; 以及设置在第二绝缘层上的顶层。此外，可以在顶层上形成第一栅电极，并且可以在非单晶半导体层中形成第二栅电极。本发明还提供了制造这种基材的方法。

3. 发明申请

WO2007133358A3 SEMICONDUCTOR BUFFER STRUCTURES 审中-公开
公开(公告)号：WO2007133358A3
公开(公告)日：2008-01-10
申请号：PCT/US2007008879
申请日：2007-04-09
申请人： SOITEC SILICON ON INSULATOR , CODY NYLES W , ARENA CHANTEL , TOMASINI PIERRE , MAZURE CARLOS
发明人： CODY NYLES W , ARENA CHANTEL , TOMASINI PIERRE , MAZURE CARLOS
IPC分类号： C23C16/22 , C23C16/24 , C23C16/455 , C30B25/02 , C30B25/14 , C30B29/02 , C30B29/06
CPC分类号： C23C16/22 , C23C16/24 , C23C16/45523 , C30B25/165 , C30B29/52
摘要： Pile ups of threading dislocations in thick graded buffer layer are reduced by enhancing dislocation gliding. During formation of a graded SiGe buffer layer, deposition of SiGe from a silicon precursor and a germanium precursor is interrupted one or more times with periods in which the flow of the silicon precursor to the substrate is stopped while the flow of the germanium precursor to the substrate is maintained.
摘要翻译：通过增强位错滑行，减少厚度梯度缓冲层穿透位错的堆积。在形成渐变的SiGe缓冲层期间，SiGe从硅前体和锗前体的沉积被中断一次或多次，其中停止向硅衬底的硅前体的流动，同时锗前体流向保持底物。

4. 发明申请

WO03017357A8 METHOD FOR OBTAINING A SELF-SUPPORTED SEMICONDUCTOR THIN FILM FOR ELECTRONIC CIRCUITS 审中-公开
标题翻译：获得电子电路自支撑半导体薄膜的方法
公开(公告)号：WO03017357A8
公开(公告)日：2003-04-03
申请号：PCT/FR0202879
申请日：2002-08-14
申请人： SOITEC SILICON ON INSULATOR , RAYSSAC OLIVIER , MAZURE CARLOS , GHYSELEN BRUNO
发明人： RAYSSAC OLIVIER , MAZURE CARLOS , GHYSELEN BRUNO
IPC分类号： H01L21/304 , H01L21/762
CPC分类号： H01L21/76254
摘要： The invention concerns a method for obtaining a self-supported thin film made of a semiconductor material, supporting at least an electronic component and/or circuit (3) one of its surfaces, from a wafer (1) of said material, the latter including a front side (2), supporting or designed to support at least an electronic component and/or circuit (3) and a rear side (4'). Said method is characterised in that it comprises steps which consist in: a) implanting atomic species inside said wafer (1), from its rear side (4, 4'), so as to obtain a weakened zone (5) delimiting a front part (6) extending from said front side (2) to said weakened zone (5) and a rear part (7) formed by the rest of the wafer (1); d) removing said rear part (7), the front part (6); repeating, if required, steps a) and b) on the rear side of said front part (6) until the latter has the desired thickness for forming said self-supported thin film.
摘要翻译：本发明涉及从所述材料的晶片（1）获得由半导体材料制成的自支撑薄膜的方法，所述半导体材料至少支撑其表面之一的电子部件和/或电路（3），所述晶片包括支撑或设计成支撑至少电子部件和/或电路（3）和后侧（4'）的前侧（2）。所述方法的特征在于其包括以下步骤：a）从其后侧（4,4'）将所述晶片（1）内的原子物质注入，以获得限定前部的弱化区（5）（6）从所述前侧（2）延伸到所述弱化区（5）和由所述晶片（1）的其余部分形成的后部（7）; d）去除所述后部（7），前部（6）; 如果需要，在所述前部（6）的后侧重复步骤a）和b），直到后者具有用于形成所述自支撑薄膜的所需厚度。

5. 发明申请

WO2010015401A3 RELAXATION OF STRAINED LAYERS 审中-公开
标题翻译：松弛应变层
公开(公告)号：WO2010015401A3
公开(公告)日：2010-05-14
申请号：PCT/EP2009005694
申请日：2009-08-06
申请人： SOITEC SILICON ON INSULATOR , LETERTRE FABRICE , MAZURE CARLOS , KRAMES MICHAEL R , MCLAURIN MELVIN B , GARDNER NATHAN F
发明人： LETERTRE FABRICE , MAZURE CARLOS , KRAMES MICHAEL R , MCLAURIN MELVIN B , GARDNER NATHAN F
IPC分类号： H01L21/324 , B01J3/00 , B01J3/06 , H01L21/20 , H01L33/00 , H01L33/32
CPC分类号： H01L21/2007 , H01L21/02422 , H01L21/02458 , H01L21/0254 , H01L21/02658 , H01L21/3245 , H01L33/0095
摘要： The present invention relates to a method for relaxing a strained material layer, comprising depositing a first low-viscosity layer comprising a first compliant material on the strained material layer, depositing a second low-viscosity layer comprising a second compliant material on the strained material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that reflow of the first and the second low-viscosity layers is caused thereby at least partly relaxing the strained material layer.
摘要翻译：本发明涉及用于松弛应变材料层的方法，该方法包括在应变材料层上沉积包括第一柔性材料的第一低粘度层，在应变材料层上沉积包括第二柔性材料的第二低粘度层以形成第一夹层结构并使第一夹层结构经受热处理，从而引起第一和第二低粘度层的回流，从而至少部分地松弛应变材料层。

6. 发明申请

WO2009112894A1 SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER 审中-公开
标题翻译：具有绝缘层的充电区的基底
公开(公告)号：WO2009112894A1
公开(公告)日：2009-09-17
申请号：PCT/IB2008052203
申请日：2008-03-13
申请人： SOITEC SILICON ON INSULATOR , ALLIBERT FREDERIC , GAUDIN GWELTAZ , LALLEMENT FABRICE , LANDRU DIDIER , LANDRY KARINE , SHAHEEN MOHAMAD , MAZURE CARLOS
发明人： ALLIBERT FREDERIC , GAUDIN GWELTAZ , LALLEMENT FABRICE , LANDRU DIDIER , LANDRY KARINE , SHAHEEN MOHAMAD , MAZURE CARLOS
IPC分类号： H01L29/78
CPC分类号： H01L29/78603 , H01L29/32 , H01L29/7841 , H01L31/0248
摘要： The invention relates to a substrate comprising successively a base wafer (1), an insulating layer (2) and a top semiconductor layer (3), characterised in that the insulating layer (2) comprises at least a zone wherein the density of charges is in absolute value higher than 1010 charges/cm2. The invention also relates to a process for making such a substrate.
摘要翻译：本发明涉及一种基板，包括连续的基底晶片（1），绝缘层（2）和顶部半导体层（3），其特征在于绝缘层（2）至少包括电荷密度为绝对值高于1010电荷/ cm2。本发明还涉及制造这种基材的方法。

7. 发明申请

WO2007017763A3 METHOD OF PRODUCTION OF A FILM 审中-公开
标题翻译：制作薄膜的方法
公开(公告)号：WO2007017763A3
公开(公告)日：2007-04-19
申请号：PCT/IB2006003071
申请日：2006-07-06
申请人： SOITEC SILICON ON INSULATOR , AULNETTE CECILE , CAYREFOURCQ IAN , MAZURE CARLOS
发明人： AULNETTE CECILE , CAYREFOURCQ IAN , MAZURE CARLOS
IPC分类号： H01L21/762
CPC分类号： H01L21/76254
摘要： The invention relates to a method of producing a film intended for applications in electronics, optics or optronics starting from an initial wafer, which includes a step of implanting atomic species through one of the faces of the wafer, which method comprises the following stages: (a) formation of a step of determined height around the periphery of the wafer, the mean thickness of the wafer at the step being less than the mean thickness of the rest of the wafer; (b) protection of said step against the implantation of atomic species; and (c) implantation of atomic species through that face of the wafer having said step, so as to form an implanted zone at a determined implant depth, said film being determined, on one side, by the implanted face of the wafer and, on the other side, by the implanted zone. The invention also relates to a wafer obtained by said method.
摘要翻译：本发明涉及一种从初始晶片开始制造用于电子学，光学或光电子学中的薄膜的方法，其包括通过晶片的一个面注入原子物质的步骤，该方法包括以下阶段：（ a）形成围绕晶片周边的确定高度的步骤，该步骤的晶片的平均厚度小于晶片的其余部分的平均厚度; （b）防止所述步骤抵抗原子物种的植入; 和（c）通过具有所述步骤的晶片的表面植入原子物质，以便在确定的植入深度形成注入区，所述膜的一侧由晶片的植入面确定，并且在另一边，由植入区。本发明还涉及通过所述方法获得的晶片。

8. 发明申请

WO03062507A2 METHOD FOR MANUFACTURING A FREE-STANDING SUBSTRATE MADE OF MONOCRYSTALLINE SEMI-CONDUCTOR MATERIAL 审中-公开
标题翻译：制造单晶半导体材料自由基底的方法
公开(公告)号：WO03062507A2
公开(公告)日：2003-07-31
申请号：PCT/EP0300693
申请日：2003-01-21
申请人： S O I TEC SILICON INSULATOR TE , GHYSELEN BRUNO , LETERTRE FABRICE , MAZURE CARLOS
发明人： GHYSELEN BRUNO , LETERTRE FABRICE , MAZURE CARLOS
IPC分类号： C30B29/38 , C23C16/01 , C23C16/34 , C30B25/02 , C30B29/04 , H01L21/20 , H01L21/762 , C30B29/40 , C23C16/27
CPC分类号： H01L21/76254 , Y10S438/977
摘要： The invention relates to a method for manufacturing a free−standing substrate made of monocrystalline semi−conductor material.This method is characterized by the following steps comprising: − transferring of a thin nucleation layer (5, 5') onto a support (7) by creating between the two a removable bonding interface (9) ;− growing by epitaxy on said thin nucleation layer (5, 5'), a microcrystalline layer (10) of material intended to comprise said substrate, until it attains a sufficient thickness to be free−standing, while preserving the removable character of the bonding interface (9) ; the coefficients of thermal expansion of the material of the thick layer (10) and of the support material (7) being chosen to be different from each other, such that at the time of cooling of the assembly, the stresses induced by differential thermal expansion between the support material (7) and that of the thick layer (10) causing the removal of said nucleation layer (5, 5') and said monocrystalline thick layer (10) from said support (7) at the level of said removable bonding interface (9).
摘要翻译：本发明涉及用于制造由单晶半导体材料制成的独立基板的方法。该方法的特征在于包括以下步骤：将薄的成核层（5,5'）转移到支撑体（7）上，通过在两个之间形成可移除的结合界面（9）; - 通过在所述薄成核层（5,5'）上的外延生长旨在包含所述基底的材料的微晶层（10），直到达到足够的厚度同时保持粘合界面（9）的可拆卸特征; 厚层（10）和支撑材料（7）的材料的热膨胀系数被选择为彼此不同，使得在组件冷却时，由不同热膨胀引起的应力在所述支撑材料（7）和所述厚层（10）的所述支撑材料（7）之间的所述可去除粘合的水平处从所述支撑体（7）移除所述成核层（5,5'）和所述单晶厚层（10）界面（9）。

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