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1. 发明申请

WO2010025074A1 LATCH-BASED IMPLEMENTATION OF A REGISTER FILE FOR A MULTI-THREADED PROCESSOR 审中-公开
标题翻译：用于多线程处理器的寄存器文件的基于锁存器的实现
公开(公告)号：WO2010025074A1
公开(公告)日：2010-03-04
申请号：PCT/US2009/054421
申请日：2009-08-20
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan , NACER, Gary , WANG, Shenghong
发明人： MOUDGILL, Mayan , NACER, Gary , WANG, Shenghong
IPC分类号： G06F15/76
CPC分类号： G06F9/30141 , G06F9/30116 , G06F9/30123
摘要： A processor register file for a multi-threaded processor is described. The processore register file includes, in one embodiment, T threads, having N b-bit wide registers. Each of the registers includes a b-bit master latch, T b-bit slave latches connected to the master latch, and a slave latch write enable connected to the slave latches. The master latch is not opened at the same time as the slave latches. In addition, only one of the slave latches is enabled at any given time. As should be apparent to those skilled in the art, T, N, and b are all integers. Other embodiments and variations are also provided.
摘要翻译：描述用于多线程处理器的处理器寄存器文件。在一个实施例中，处理器寄存器文件包括具有N个b位宽寄存器的T线程。每个寄存器包括一个b位主锁存器，连接到主锁存器的T b位从属锁存器和一个从锁存器写使能，连接到从锁存器。主锁存器不会与从动锁存器同时打开。此外，在任何给定时间只有一个从锁存器被使能。对于本领域技术人员来说显而易见的是，T，N和b都是整数。还提供了其他实施例和变型。

2. 发明申请

WO2009146241A1 POWER SAVING CIRCUIT USING A CLOCK BUFFER AND MULTIPLE FLIP-FLOPS 审中-公开
标题翻译：节电电路使用时钟缓冲器和多个FLIP-FLOPS
公开(公告)号：WO2009146241A1
公开(公告)日：2009-12-03
申请号：PCT/US2009/043175
申请日：2009-05-07
申请人： SANDBRIDGE TECHNOLOGIES, INC. , NACER, Gary , WANG, Shenghong , MOUDGILL, Mayan
发明人： NACER, Gary , WANG, Shenghong , MOUDGILL, Mayan
IPC分类号： G06F1/00
CPC分类号： G06F1/32 , G06F1/04 , Y10T29/49117
摘要： A circuit is described including a clock input for at least one clock signal. Only one clock buffer is connected to the clock input to generate, based on the at least one clock signal, at least a first modified clock signal and a second modified clock signal. A plurality of flip-flops are connected to the clock buffer. Each of the flip-flops receive the first and second modified clock signals. A plurality of data inputs are each connected to at least one of the plurality of flip-flops to provide input data to the plurality of flip-flops. A plurality of data outputs each are connected to at least one of the plurality of flip-flops to provide output data from the plurality of flip-flops. Each of the plurality of flip-flops transform the input data to the output data utilizing the first modified clock signal and the second modified clock signal.
摘要翻译：描述了包括用于至少一个时钟信号的时钟输入的电路。只有一个时钟缓冲器被连接到时钟输入端，以便基于至少一个时钟信号产生至少第一修改时钟信号和第二修改时钟信号。多个触发器连接到时钟缓冲器。每个触发器接收第一和第二修改的时钟信号。多个数据输入各自连接到多个触发器中的至少一个，以向多个触发器提供输入数据。多个数据输出各自连接到多个触发器中的至少一个，以提供来自多个触发器的输出数据。多个触发器中的每一个利用第一修改时钟信号和第二修改时钟信号将输入数据变换为输出数据。

3. 发明申请

WO2010017263A1 HALTABLE AND RESTARTABLE DMA ENGINE 审中-公开
标题翻译：易燃和可重启的DMA发动机
公开(公告)号：WO2010017263A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/052794
申请日：2009-08-05
申请人： SANDBRIDGE TECHNOLOGIES, INC. , MOUDGILL, Mayan , WANG, Shenghong
发明人： MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.
摘要翻译：描述了用于DMA引擎的操作的方法。启动复制以将第一数量的字节从第一源存储器位置传送到第一目的地存储器位置。然后，在第一个字节数被复制之前发出停止指令。复制停止后，建立第二个字节数，包含剩下的要复制的字节。传输停止后，识别出第二个字节数量。然后生成和存储数量信息。识别第二源存储器位置以指示第二数量的字节存储在哪里。然后生成并存储第二源存储器位置信息。然后识别第二目的地存储器位置以指示要传送第二数量字节的位置。然后生成并存储第二目的地存储器位置信息。

4. 发明申请

WO2015119886A1 METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS 审中-公开
标题翻译：使用处理器生成管道控制信号的方法和装置
公开(公告)号：WO2015119886A1
公开(公告)日：2015-08-13
申请号：PCT/US2015/014064
申请日：2015-02-02
申请人： OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC. , GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Murugappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
发明人： GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Murugappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
IPC分类号： H04W72/12
CPC分类号： G06F9/3822 , G06F9/3836 , G06F9/3853
摘要： A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.
摘要翻译：计算机处理器的链接位解码器接收指令流。链接位解码器从指令流中选择一组指令。链接位解码器从指令流的每个指令中提取指定的位以产生一系列链接位。链接位解码器解码链接序列。考虑到解码的链接序列，链接位解码器识别所选择的指令组之中的零个或多个指令流相关性。链接位解码器输出控制信号以使得处理器的一个或多个管线级鉴于所述组指令序列中所识别的零个或多个指令流依赖性来执行所选择的指令组。

5. 发明申请

WO2003102780A1 METHOD AND APPARATUS FOR MULTITHREADED CACHE WITH CACHE EVICTION BASED ON THREAD IDENTIFIER 审中-公开
标题翻译：基于螺纹识别器的多速缓存高速缓存的方法和设备
公开(公告)号：WO2003102780A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/017332
申请日：2003-06-03
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , GLOSSNER, John, C. , HOANE, Arthur, Joseph , MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0842 , G06F12/128
摘要： A cache memory for use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches (400’) each implementing a thread-based eviction process that reduces the amount of replacement policy storage required in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array (402) having multiple sets (set 1-set 4) of memory locations, and a directory (404) for storing tags (404-k) each corresponding to at least a portion of a particular address of one of the memory locations. The directory (404) has multiple entries each storing multiple ones of the tags (404-k), such that if there are n sets of memory locations in the memory array, there are n tags (404-k) associated with each directory entry. The directory (404) is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of a thread identifier of the given thread cache.
摘要翻译：用于多线程处理器的高速缓存存储器包括多个设置关联线程高速缓冲存储器，其中一个或多个线程高速缓冲存储器（400'）各自实现基于线程的逐出过程，该过程减少了在高速缓存存储器。在说明性实施例中的至少一个线程高速缓存中的给定的一个包括具有存储器位置的多个集合（集合1集合4）的存储器阵列（402）和用于存储每个对应的标签（404-k）的目录（404）到存储器位置之一的特定地址的至少一部分。目录（404）具有多个条目，每个条目存储多个标签（404-k），使得如果存储器阵列中存在n组存储器位置，则存在与每个目录条目相关联的n个标签（404-k）。目录（404）被用于实现访问请求和存储器阵列的存储器位置之间的集合关联地址映射。至少部分地基于给定线程高速缓存的线程标识符的至少一部分，选择存储器位置中的特定一个存储器位置中的入口与给定的线程高速缓存结合高速缓存未命中事件进行驱逐。

6. 发明申请

WO2003102781A1 METHOD AND APPARATUS FOR MULTITHREADED CACHE WITH SIMPLIFIED IMPLEMENTATION OF CACHE REPLACEMENT POLICY 审中-公开
标题翻译：多媒体缓存的方法和设备，具有简化的缓存更新策略的实现
公开(公告)号：WO2003102781A1
公开(公告)日：2003-12-11
申请号：PCT/US2003/017345
申请日：2003-06-03
申请人： SANDBRIDGE TECHNOLOGIES, INC.
发明人： HOKENEK, Erdem , GLOSSNER, John, C. , HOANE, Arthur Joseph , MOUDGILL, Mayan , WANG, Shenghong
IPC分类号： G06F12/00
CPC分类号： G06F12/0842 , G06F12/0864 , G06F12/123 , G06F12/126 , Y02D10/13
摘要： A cache memory for the use in a multithreaded processor includes a number of set-associative thread caches, with one or more of the thread caches each implementing an eviction process based on access request address that reduces the amount of replacement policy storage requires in the cache memory. At least a given one of the thread caches in an illustrative embodiment includes a memory array having multiple sets of memory locations, and a directory for storing tags each corresponding to at least a portion of a particular address of one of the memory locations. The directory has a multiple of entries each storing multiple ones of the tags, such that if there are n sets of memory locations in the memory array, there are n tags associated with each directory entry. The directory is utilized in implementing a set-associative address mapping between access requests and memory locations of the memory array. An entry in a particular one of the memory locations is selected for eviction from the given thread cache in conjunction with a cache miss event, based at least in part on at least a portion of an address in access request associated with the cache miss event.
摘要翻译：用于多线程处理器的高速缓存存储器包括多个集合关联线程高速缓冲存储器，其中一个或多个线程高速缓冲存储器基于访问请求地址实现驱逐过程，该访问请求地址减少了高速缓存中替换策略存储所需的量记忆。在说明性实施例中的至少一个线程高速缓存中的给定的一个包括具有多组存储器位置的存储器阵列和用于存储标签的目录，每个对应于存储器位置之一的特定地址的至少一部分。目录具有多个条目，每个条目存储多个标签，使得如果存储器阵列中存在n组存储器位置，则存在与每个目录条目相关联的n个标签。该目录用于实现访问请求和存储器阵列的存储器位置之间的集合关联地址映射。至少部分地基于与高速缓存未命中事件相关联的访问请求中的地址的至少一部分，选择存储器位置中的特定一个存储器位置中的条目与来自给定线程高速缓存的结合高速缓存未命中事件的逐出。

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